mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-17 16:14:25 +08:00
1009aa1205
This tag contains some major improvements to the RISC-V port, including the necessary interrupt controller and timer support to actually make it to userspace. Support for three devices has been added: * Support for the ISA-mandated timers on RISC-V systems. * Support for the ISA-mandated first-level interrupt controller on RISC-V systems, which is handled as part of our core arch code because it's very small and tightly tied to the ISA. * Support for SiFive's platform-level interrupt controller, which talks to the actual devices. In addition to these new devices, there are a handful of cleanups all over the RISC-V tree: * Build fixes for various configurations * A fix to the vDSO build's makefile so it respects CFLAGS. * The addition of __lshrti3, a libgcc derived function necessary for some 32-bit configurations. * !SMP && PERF_EVENTS * Cleanups to the arch code to remove the remnants of old versions of the drivers that were just properly submitted. * Some dead code from the timer driver, most of which wasn't ever even compiled. * Cleanups of some interrupt #defines, which are now local to the interrupt handling code. * Fixes to ptrace(), which while not being sufficient to fully make GDB work are at least sufficient to get simple GDB tasks to work. * Early printk support via RISC-V's architecturally mandated SBI console device. * A fix to our early debug trap handler to ensure it's always aligned. These patches have all been through a fairly extensive review process, but as this enables a whole pile of functionality (ie, userspace) I'm confident we'll need to submit a few more patches. The only concrete issues I know about are the sys_riscv_flush_icache patches, but as I managed to screw those up on Friday I figured it'd be best to let them bake another week. This tag boots a Fedora root filesystem on QEMU's master branch for me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on the HiFive Unleashed. Thanks to Christoph Hellwig and the other guys at WD for getting the new drivers in shape! -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAltx3HcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRDvTKFQLMurQc7nEACh8NCRLyXHOAQefomb+BUx+DJXweau lhTiPexB7+3ZAT6FvL8BgHFu3qMsgZ8iI5pxIz7tap2WRTlakRABLes7c3xQPI4a 3rDbZFE78lQDNY0Kj8iUpvYr0aOfMcC8aoD30qQHaWZVgYZvaZGD3Sar6VbTyaNe 5F5lRaiAtrMmHNio/fXQvnMP83nc1Nxzc4q8VeRjmufc0CvGZUs3L2ZRVx1phwav VedQFsrNHlcyulBv9rQXzaeyvVn+FNKlu4c/9sI6xsGZofGZjOqub1vjURuEfTc5 4AtdFMN0Xb2TYCK277Fr/FY/VEHGXCV+3hGc2U62hnpBtRgGERn7gQUimCJD5b+V gpXZGjtLvTXp9a4N6+ThC/oqvr72aLzInNap95MFK5xSMx/4AdCG7u63sd2qLtkL tlYho+Hd50ImIlUCTs6pfjzmgTMLW2huVJhDNx2lt9OUvNNYjTc4mjEK2WK8DUC7 aUMcHYZMn3hJFNwvd5xTxLPua4ahhhYTyfzHwnMiND4ZjdUnxtrKNj46HjSPqMp9 mgKOkv3G0a021gYODI/dweYI1SV2my814fQHZW4rcFYM2lLwrn2cPMMGezAJF9sR mbLHW6ZxJrtd9m+RZsJB9Z3QnBs68yIqTOBPRRFM5egwt9s9y+19HnBDVe1hj8/j OpmZ/qXCqQt+jA== =PfnC -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux Pull RISC-V updates from Palmer Dabbelt: "This contains some major improvements to the RISC-V port, including the necessary interrupt controller and timer support to actually make it to userspace. Support for three devices has been added: - the ISA-mandated timers on RISC-V systems. - the ISA-mandated first-level interrupt controller on RISC-V systems, which is handled as part of our core arch code because it's very small and tightly tied to the ISA. - SiFive's platform-level interrupt controller, which talks to the actual devices. In addition to these new devices, there are a handful of cleanups all over the RISC-V tree: - build fixes for various configurations: * A fix to the vDSO build's makefile so it respects CFLAGS. * The addition of __lshrti3, a libgcc derived function necessary for some 32-bit configurations. * !SMP && PERF_EVENTS - Cleanups to the arch code to remove the remnants of old versions of the drivers that were just properly submitted. * Some dead code from the timer driver, most of which wasn't ever even compiled. * Cleanups of some interrupt #defines, which are now local to the interrupt handling code. - Fixes to ptrace(), which while not being sufficient to fully make GDB work are at least sufficient to get simple GDB tasks to work. - Early printk support via RISC-V's architecturally mandated SBI console device. - A fix to our early debug trap handler to ensure it's always aligned. These patches have all been through a fairly extensive review process, but as this enables a whole pile of functionality (ie, userspace) I'm confident we'll need to submit a few more patches. The only concrete issues I know about are the sys_riscv_flush_icache patches, but as I managed to screw those up on Friday I figured it'd be best to let them bake another week. This tag boots a Fedora root filesystem on QEMU's master branch for me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on the HiFive Unleashed. Thanks to Christoph Hellwig and the other guys at WD for getting the new drivers in shape!" * tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller dt-bindings: interrupt-controller: RISC-V local interrupt controller RISC-V: Fix !CONFIG_SMP compilation error irqchip: add a SiFive PLIC driver RISC-V: Add the directive for alignment of stvec's value clocksource: new RISC-V SBI timer driver RISC-V: implement low-level interrupt handling RISC-V: add a definition for the SIE SEIE bit RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h RISC-V: simplify software interrupt / IPI code RISC-V: remove timer leftovers RISC-V: Add early printk support via the SBI console RISC-V: Don't increment sepc after breakpoint. RISC-V: implement __lshrti3. RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO
387 lines
7.2 KiB
Plaintext
387 lines
7.2 KiB
Plaintext
menu "IRQ chip support"
|
|
|
|
config IRQCHIP
|
|
def_bool y
|
|
depends on OF_IRQ
|
|
|
|
config ARM_GIC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
select GENERIC_IRQ_MULTI_HANDLER
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
|
|
|
config ARM_GIC_PM
|
|
bool
|
|
depends on PM
|
|
select ARM_GIC
|
|
select PM_CLK
|
|
|
|
config ARM_GIC_MAX_NR
|
|
int
|
|
default 2 if ARCH_REALVIEW
|
|
default 1
|
|
|
|
config ARM_GIC_V2M
|
|
bool
|
|
depends on PCI
|
|
select ARM_GIC
|
|
select PCI_MSI
|
|
|
|
config GIC_NON_BANKED
|
|
bool
|
|
|
|
config ARM_GIC_V3
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_MULTI_HANDLER
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
select PARTITION_PERCPU
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
|
|
|
config ARM_GIC_V3_ITS
|
|
bool
|
|
select GENERIC_MSI_IRQ_DOMAIN
|
|
default ARM_GIC_V3
|
|
|
|
config ARM_GIC_V3_ITS_PCI
|
|
bool
|
|
depends on ARM_GIC_V3_ITS
|
|
depends on PCI
|
|
depends on PCI_MSI
|
|
default ARM_GIC_V3_ITS
|
|
|
|
config ARM_GIC_V3_ITS_FSL_MC
|
|
bool
|
|
depends on ARM_GIC_V3_ITS
|
|
depends on FSL_MC_BUS
|
|
default ARM_GIC_V3_ITS
|
|
|
|
config ARM_NVIC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
config ARM_VIC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_MULTI_HANDLER
|
|
|
|
config ARM_VIC_NR
|
|
int
|
|
default 4 if ARCH_S5PV210
|
|
default 2
|
|
depends on ARM_VIC
|
|
help
|
|
The maximum number of VICs available in the system, for
|
|
power management.
|
|
|
|
config ARMADA_370_XP_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select PCI_MSI if PCI
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
|
|
|
config ALPINE_MSI
|
|
bool
|
|
depends on PCI
|
|
select PCI_MSI
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
config ATMEL_AIC_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_MULTI_HANDLER
|
|
select SPARSE_IRQ
|
|
|
|
config ATMEL_AIC5_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_MULTI_HANDLER
|
|
select SPARSE_IRQ
|
|
|
|
config I8259
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config BCM6345_L1_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
|
|
|
config BCM7038_L1_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
|
|
|
config BCM7120_L2_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config BRCMSTB_L2_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config DW_APB_ICTL
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config FARADAY_FTINTC010
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_MULTI_HANDLER
|
|
select SPARSE_IRQ
|
|
|
|
config HISILICON_IRQ_MBIGEN
|
|
bool
|
|
select ARM_GIC_V3
|
|
select ARM_GIC_V3_ITS
|
|
|
|
config IMGPDC_IRQ
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config IRQ_MIPS_CPU
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
|
|
select IRQ_DOMAIN
|
|
select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
|
|
|
config CLPS711X_IRQCHIP
|
|
bool
|
|
depends on ARCH_CLPS711X
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_MULTI_HANDLER
|
|
select SPARSE_IRQ
|
|
default y
|
|
|
|
config OMPIC
|
|
bool
|
|
|
|
config OR1K_PIC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config OMAP_IRQCHIP
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config ORION_IRQCHIP
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_MULTI_HANDLER
|
|
|
|
config PIC32_EVIC
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config JCORE_AIC
|
|
bool "J-Core integrated AIC" if COMPILE_TEST
|
|
depends on OF
|
|
select IRQ_DOMAIN
|
|
help
|
|
Support for the J-Core integrated AIC.
|
|
|
|
config RENESAS_INTC_IRQPIN
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config RENESAS_IRQC
|
|
bool
|
|
select GENERIC_IRQ_CHIP
|
|
select IRQ_DOMAIN
|
|
|
|
config ST_IRQCHIP
|
|
bool
|
|
select REGMAP
|
|
select MFD_SYSCON
|
|
help
|
|
Enables SysCfg Controlled IRQs on STi based platforms.
|
|
|
|
config TANGO_IRQ
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
config TB10X_IRQC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
config TS4800_IRQ
|
|
tristate "TS-4800 IRQ controller"
|
|
select IRQ_DOMAIN
|
|
depends on HAS_IOMEM
|
|
depends on SOC_IMX51 || COMPILE_TEST
|
|
help
|
|
Support for the TS-4800 FPGA IRQ controller
|
|
|
|
config VERSATILE_FPGA_IRQ
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config VERSATILE_FPGA_IRQ_NR
|
|
int
|
|
default 4
|
|
depends on VERSATILE_FPGA_IRQ
|
|
|
|
config XTENSA_MX
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
|
|
|
|
config XILINX_INTC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config IRQ_CROSSBAR
|
|
bool
|
|
help
|
|
Support for a CROSSBAR ip that precedes the main interrupt controller.
|
|
The primary irqchip invokes the crossbar's callback which inturn allocates
|
|
a free irq and configures the IP. Thus the peripheral interrupts are
|
|
routed to one of the free irqchip interrupt lines.
|
|
|
|
config KEYSTONE_IRQ
|
|
tristate "Keystone 2 IRQ controller IP"
|
|
depends on ARCH_KEYSTONE
|
|
help
|
|
Support for Texas Instruments Keystone 2 IRQ controller IP which
|
|
is part of the Keystone 2 IPC mechanism
|
|
|
|
config MIPS_GIC
|
|
bool
|
|
select GENERIC_IRQ_IPI
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
select MIPS_CM
|
|
|
|
config INGENIC_IRQ
|
|
bool
|
|
depends on MACH_INGENIC
|
|
default y
|
|
|
|
config RENESAS_H8300H_INTC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config RENESAS_H8S_INTC
|
|
bool
|
|
select IRQ_DOMAIN
|
|
|
|
config IMX_GPCV2
|
|
bool
|
|
select IRQ_DOMAIN
|
|
help
|
|
Enables the wakeup IRQs for IMX platforms with GPCv2 block
|
|
|
|
config IRQ_MXS
|
|
def_bool y if MACH_ASM9260 || ARCH_MXS
|
|
select IRQ_DOMAIN
|
|
select STMP_DEVICE
|
|
|
|
config MSCC_OCELOT_IRQ
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
config MVEBU_GICP
|
|
bool
|
|
|
|
config MVEBU_ICU
|
|
bool
|
|
|
|
config MVEBU_ODMI
|
|
bool
|
|
select GENERIC_MSI_IRQ_DOMAIN
|
|
|
|
config MVEBU_PIC
|
|
bool
|
|
|
|
config LS_SCFG_MSI
|
|
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
|
|
depends on PCI && PCI_MSI
|
|
|
|
config PARTITION_PERCPU
|
|
bool
|
|
|
|
config EZNPS_GIC
|
|
bool "NPS400 Global Interrupt Manager (GIM)"
|
|
depends on ARC || (COMPILE_TEST && !64BIT)
|
|
select IRQ_DOMAIN
|
|
help
|
|
Support the EZchip NPS400 global interrupt controller
|
|
|
|
config STM32_EXTI
|
|
bool
|
|
select IRQ_DOMAIN
|
|
select GENERIC_IRQ_CHIP
|
|
|
|
config QCOM_IRQ_COMBINER
|
|
bool "QCOM IRQ combiner support"
|
|
depends on ARCH_QCOM && ACPI
|
|
select IRQ_DOMAIN
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
help
|
|
Say yes here to add support for the IRQ combiner devices embedded
|
|
in Qualcomm Technologies chips.
|
|
|
|
config IRQ_UNIPHIER_AIDET
|
|
bool "UniPhier AIDET support" if COMPILE_TEST
|
|
depends on ARCH_UNIPHIER || COMPILE_TEST
|
|
default ARCH_UNIPHIER
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
help
|
|
Support for the UniPhier AIDET (ARM Interrupt Detector).
|
|
|
|
config MESON_IRQ_GPIO
|
|
bool "Meson GPIO Interrupt Multiplexer"
|
|
depends on ARCH_MESON
|
|
select IRQ_DOMAIN
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
help
|
|
Support Meson SoC Family GPIO Interrupt Multiplexer
|
|
|
|
config GOLDFISH_PIC
|
|
bool "Goldfish programmable interrupt controller"
|
|
depends on MIPS && (GOLDFISH || COMPILE_TEST)
|
|
select IRQ_DOMAIN
|
|
help
|
|
Say yes here to enable Goldfish interrupt controller driver used
|
|
for Goldfish based virtual platforms.
|
|
|
|
config QCOM_PDC
|
|
bool "QCOM PDC"
|
|
depends on ARCH_QCOM
|
|
select IRQ_DOMAIN
|
|
select IRQ_DOMAIN_HIERARCHY
|
|
help
|
|
Power Domain Controller driver to manage and configure wakeup
|
|
IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
|
|
|
|
endmenu
|
|
|
|
config SIFIVE_PLIC
|
|
bool "SiFive Platform-Level Interrupt Controller"
|
|
depends on RISCV
|
|
help
|
|
This enables support for the PLIC chip found in SiFive (and
|
|
potentially other) RISC-V systems. The PLIC controls devices
|
|
interrupts and connects them to each core's local interrupt
|
|
controller. Aside from timer and software interrupts, all other
|
|
interrupt sources are subordinate to the PLIC.
|
|
|
|
If you don't know what to do here, say Y.
|