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c83a917112
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Steven Miao <realmz6@gmail.com>
501 lines
13 KiB
C
501 lines
13 KiB
C
/*
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* arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __MEM_INIT_H__
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#define __MEM_INIT_H__
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#if defined(EBIU_SDGCTL)
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#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
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defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
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defined(CONFIG_MEM_MT48LC32M8A2_75) || \
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defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
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defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC32M8A2_75)
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#if (CONFIG_SCLK_HZ > 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_7
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#define SDRAM_tRAS_num 7
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_6
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#define SDRAM_tRAS_num 6
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_5
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#define SDRAM_tRAS_num 5
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_2
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#define SDRAM_tRAS_num 2
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ <= 29850746)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_1
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#define SDRAM_tRAS_num 1
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#endif
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/*
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* The BF526-EZ-Board changed SDRAM chips between revisions,
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* so we use below timings to accommodate both.
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*/
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#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
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#if (CONFIG_SCLK_HZ > 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_8
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#define SDRAM_tRAS_num 8
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_7
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#define SDRAM_tRAS_num 7
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_6
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#define SDRAM_tRAS_num 6
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_5
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#define SDRAM_tRAS_num 5
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_2
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_4
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#define SDRAM_tRAS_num 4
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_3
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#define SDRAM_tRAS_num 3
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#if (CONFIG_SCLK_HZ <= 29850746)
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#define SDRAM_tRP TRP_1
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#define SDRAM_tRP_num 1
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#define SDRAM_tRAS TRAS_2
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#define SDRAM_tRAS_num 2
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#define SDRAM_tRCD TRCD_1
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#define SDRAM_tWR TWR_2
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#endif
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#endif
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#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
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defined(CONFIG_MEM_MT48LC8M32B2B5_7)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
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defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
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defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
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defined(CONFIG_MEM_MT48LC32M8A2_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_2
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#endif
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#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
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/* Equation from section 17 (p17-46) of BF533 HRM */
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#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
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/* Enable SCLK Out */
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#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
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#else
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#define mem_SDRRC CONFIG_MEM_SDRRC
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#define mem_SDGCTL CONFIG_MEM_SDGCTL
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#endif
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#endif
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#if defined(EBIU_DDRCTL0)
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#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
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#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
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#define DDR_CLK_HZ(x) (1000*1000*1000/x)
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#if defined(CONFIG_MEM_MT46V32M16_6T)
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#define DDR_SIZE DEVSZ_512
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#define DDR_WIDTH DEVWD_16
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#define DDR_MAX_tCK 13
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#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
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#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
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#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
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#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
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#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
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#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
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#define DDR_tWTR DDR_TWTR(1)
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#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
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#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
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#endif
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#if defined(CONFIG_MEM_MT46V32M16_5B)
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#define DDR_SIZE DEVSZ_512
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#define DDR_WIDTH DEVWD_16
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#define DDR_MAX_tCK 13
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#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
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#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
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#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
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#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
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#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
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#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
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#define DDR_tWTR DDR_TWTR(2)
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#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
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#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
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#endif
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#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
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# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
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#elif(CONFIG_SCLK_HZ <= 133333333)
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# define DDR_CL CL_2
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#else
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# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
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#endif
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#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
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#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
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#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
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| DDR_tMRD | DDR_tWR | DDR_tRCD)
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#define mem_DDRCTL2 DDR_CL
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#else
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#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
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#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
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#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
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#endif
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#endif
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#if defined CONFIG_CLKIN_HALF
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#define CLKIN_HALF 1
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#else
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#define CLKIN_HALF 0
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#endif
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#if defined CONFIG_PLL_BYPASS
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#define PLL_BYPASS 1
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#else
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#define PLL_BYPASS 0
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#endif
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#ifdef CONFIG_BF60x
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/* DMC status bits */
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#define IDLE 0x1
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#define MEMINITDONE 0x4
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#define SRACK 0x8
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#define PDACK 0x10
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#define DPDACK 0x20
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#define DLLCALDONE 0x2000
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#define PENDREF 0xF0000
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#define PHYRDPHASE 0xF00000
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#define PHYRDPHASE_OFFSET 20
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/* DMC control bits */
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#define LPDDR 0x2
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#define INIT 0x4
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#define SRREQ 0x8
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#define PDREQ 0x10
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#define DPDREQ 0x20
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#define PREC 0x40
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#define ADDRMODE 0x100
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#define RDTOWR 0xE00
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#define PPREF 0x1000
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#define DLLCAL 0x2000
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/* DMC DLL control bits */
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#define DLLCALRDCNT 0xFF
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#define DATACYC 0xF00
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#define DATACYC_OFFSET 8
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/* CGU Divisor bits */
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#define CSEL_OFFSET 0
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#define S0SEL_OFFSET 5
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#define SYSSEL_OFFSET 8
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#define S1SEL_OFFSET 13
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#define DSEL_OFFSET 16
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#define OSEL_OFFSET 22
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#define ALGN 0x20000000
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#define UPDT 0x40000000
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#define LOCK 0x80000000
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/* CGU Status bits */
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#define PLLEN 0x1
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#define PLLBP 0x2
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#define PLOCK 0x4
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#define CLKSALGN 0x8
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/* CGU Control bits */
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#define MSEL_MASK 0x7F00
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#define DF_MASK 0x1
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struct ddr_config {
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u32 ddr_clk;
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u32 dmc_ddrctl;
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u32 dmc_effctl;
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u32 dmc_ddrcfg;
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u32 dmc_ddrtr0;
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u32 dmc_ddrtr1;
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u32 dmc_ddrtr2;
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u32 dmc_ddrmr;
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u32 dmc_ddrmr1;
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};
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#if defined(CONFIG_MEM_MT47H64M16)
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static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
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[0] = {
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.ddr_clk = 125,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20705212,
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.dmc_ddrtr1 = 0x201003CF,
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.dmc_ddrtr2 = 0x00320107,
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.dmc_ddrmr = 0x00000422,
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.dmc_ddrmr1 = 0x4,
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},
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[1] = {
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.ddr_clk = 133,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20806313,
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.dmc_ddrtr1 = 0x2013040D,
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.dmc_ddrtr2 = 0x00320108,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[2] = {
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.ddr_clk = 150,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x20160492,
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.dmc_ddrtr2 = 0x00320209,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[3] = {
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.ddr_clk = 166,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20A07323,
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.dmc_ddrtr1 = 0x2016050E,
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.dmc_ddrtr2 = 0x00320209,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[4] = {
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.ddr_clk = 200,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20a07323,
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.dmc_ddrtr1 = 0x2016050f,
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.dmc_ddrtr2 = 0x00320509,
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.dmc_ddrmr = 0x00000632,
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.dmc_ddrmr1 = 0x4,
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},
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[5] = {
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.ddr_clk = 225,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
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.dmc_ddrcfg = 0x00000422,
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.dmc_ddrtr0 = 0x20E0A424,
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.dmc_ddrtr1 = 0x302006DB,
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.dmc_ddrtr2 = 0x0032020D,
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.dmc_ddrmr = 0x00000842,
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.dmc_ddrmr1 = 0x4,
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},
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[6] = {
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.ddr_clk = 250,
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.dmc_ddrctl = 0x00000904,
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.dmc_effctl = 0x004400C0,
|
|
.dmc_ddrcfg = 0x00000422,
|
|
.dmc_ddrtr0 = 0x20E0A424,
|
|
.dmc_ddrtr1 = 0x3020079E,
|
|
.dmc_ddrtr2 = 0x0032050D,
|
|
.dmc_ddrmr = 0x00000842,
|
|
.dmc_ddrmr1 = 0x4,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
static inline void dmc_enter_self_refresh(void)
|
|
{
|
|
if (bfin_read_DMC0_STAT() & MEMINITDONE) {
|
|
bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
|
|
while (!(bfin_read_DMC0_STAT() & SRACK))
|
|
continue;
|
|
}
|
|
}
|
|
|
|
static inline void dmc_exit_self_refresh(void)
|
|
{
|
|
if (bfin_read_DMC0_STAT() & MEMINITDONE) {
|
|
bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
|
|
while (bfin_read_DMC0_STAT() & SRACK)
|
|
continue;
|
|
}
|
|
}
|
|
|
|
static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
|
|
{
|
|
dmc_enter_self_refresh();
|
|
|
|
/* Don't set the same value of MSEL and DF to CGU_CTL */
|
|
if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
|
|
!= cgu_ctl) {
|
|
bfin_write32(CGU0_DIV, cgu_div);
|
|
bfin_write32(CGU0_CTL, cgu_ctl);
|
|
while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
|
|
!(bfin_read32(CGU0_STAT) & PLOCK))
|
|
continue;
|
|
}
|
|
|
|
bfin_write32(CGU0_DIV, cgu_div | UPDT);
|
|
while (bfin_read32(CGU0_STAT) & CLKSALGN)
|
|
continue;
|
|
|
|
dmc_exit_self_refresh();
|
|
}
|
|
|
|
static inline void init_dmc(u32 dmc_clk)
|
|
{
|
|
int i, dlldatacycle, dll_ctl;
|
|
|
|
for (i = 0; i < 7; i++) {
|
|
if (ddr_config_table[i].ddr_clk == dmc_clk) {
|
|
bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
|
|
bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
|
|
bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
|
|
bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
|
|
bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
|
|
bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
|
|
bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl);
|
|
bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
|
|
break;
|
|
}
|
|
}
|
|
|
|
while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
|
|
continue;
|
|
|
|
dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
|
|
dll_ctl = bfin_read_DMC0_DLLCTL();
|
|
dll_ctl &= ~DATACYC;
|
|
bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
|
|
|
|
while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
|
|
continue;
|
|
}
|
|
#endif
|
|
|
|
#endif /*__MEM_INIT_H__*/
|
|
|