mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-11 13:04:03 +08:00
7d38f08973
Documentation wrongly tells that book3s/32 CPU have hash MMU. 603 and e300 core only have software loaded TLB. 755, 7450 family and e600 core have both hash MMU and software loaded TLB. This can be selected by setting a bit in HID2 (755) or HID0 (others). At the time being this is not supported by the kernel. Make this explicit in the documentation. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/261923c075d1cb49d02493685e8585d4ea2a5197.1593698951.git.christophe.leroy@csgroup.eu
225 lines
6.2 KiB
ReStructuredText
225 lines
6.2 KiB
ReStructuredText
============
|
|
CPU Families
|
|
============
|
|
|
|
This document tries to summarise some of the different cpu families that exist
|
|
and are supported by arch/powerpc.
|
|
|
|
|
|
Book3S (aka sPAPR)
|
|
------------------
|
|
|
|
- Hash MMU (except 603 and e300)
|
|
- Software loaded TLB (603 and e300)
|
|
- Selectable Software loaded TLB in addition to hash MMU (755, 7450, e600)
|
|
- Mix of 32 & 64 bit::
|
|
|
|
+--------------+ +----------------+
|
|
| Old POWER | --------------> | RS64 (threads) |
|
|
+--------------+ +----------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+ +----------------+ +------+
|
|
| 601 | --------------> | 603 | ---> | e300 |
|
|
+--------------+ +----------------+ +------+
|
|
| |
|
|
| |
|
|
v v
|
|
+--------------+ +-----+ +----------------+ +-------+
|
|
| 604 | | 755 | <--- | 750 (G3) | ---> | 750CX |
|
|
+--------------+ +-----+ +----------------+ +-------+
|
|
| | |
|
|
| | |
|
|
v v v
|
|
+--------------+ +----------------+ +-------+
|
|
| 620 (64 bit) | | 7400 | | 750CL |
|
|
+--------------+ +----------------+ +-------+
|
|
| | |
|
|
| | |
|
|
v v v
|
|
+--------------+ +----------------+ +-------+
|
|
| POWER3/630 | | 7410 | | 750FX |
|
|
+--------------+ +----------------+ +-------+
|
|
| |
|
|
| |
|
|
v v
|
|
+--------------+ +----------------+
|
|
| POWER3+ | | 7450 |
|
|
+--------------+ +----------------+
|
|
| |
|
|
| |
|
|
v v
|
|
+--------------+ +----------------+
|
|
| POWER4 | | 7455 |
|
|
+--------------+ +----------------+
|
|
| |
|
|
| |
|
|
v v
|
|
+--------------+ +-------+ +----------------+
|
|
| POWER4+ | --> | 970 | | 7447 |
|
|
+--------------+ +-------+ +----------------+
|
|
| | |
|
|
| | |
|
|
v v v
|
|
+--------------+ +-------+ +----------------+
|
|
| POWER5 | | 970FX | | 7448 |
|
|
+--------------+ +-------+ +----------------+
|
|
| | |
|
|
| | |
|
|
v v v
|
|
+--------------+ +-------+ +----------------+
|
|
| POWER5+ | | 970MP | | e600 |
|
|
+--------------+ +-------+ +----------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| POWER5++ |
|
|
+--------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+ +-------+
|
|
| POWER6 | <-?-> | Cell |
|
|
+--------------+ +-------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| POWER7 |
|
|
+--------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| POWER7+ |
|
|
+--------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| POWER8 |
|
|
+--------------+
|
|
|
|
|
|
+---------------+
|
|
| PA6T (64 bit) |
|
|
+---------------+
|
|
|
|
|
|
IBM BookE
|
|
---------
|
|
|
|
- Software loaded TLB.
|
|
- All 32 bit::
|
|
|
|
+--------------+
|
|
| 401 |
|
|
+--------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| 403 |
|
|
+--------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| 405 |
|
|
+--------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| 440 |
|
|
+--------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+ +----------------+
|
|
| 450 | --> | BG/P |
|
|
+--------------+ +----------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| 460 |
|
|
+--------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| 476 |
|
|
+--------------+
|
|
|
|
|
|
Motorola/Freescale 8xx
|
|
----------------------
|
|
|
|
- Software loaded with hardware assist.
|
|
- All 32 bit::
|
|
|
|
+-------------+
|
|
| MPC8xx Core |
|
|
+-------------+
|
|
|
|
|
|
Freescale BookE
|
|
---------------
|
|
|
|
- Software loaded TLB.
|
|
- e6500 adds HW loaded indirect TLB entries.
|
|
- Mix of 32 & 64 bit::
|
|
|
|
+--------------+
|
|
| e200 |
|
|
+--------------+
|
|
|
|
|
|
+--------------------------------+
|
|
| e500 |
|
|
+--------------------------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------------------------+
|
|
| e500v2 |
|
|
+--------------------------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------------------------+
|
|
| e500mc (Book3e) |
|
|
+--------------------------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------------------------+
|
|
| e5500 (64 bit) |
|
|
+--------------------------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------------------------+
|
|
| e6500 (HW TLB) (Multithreaded) |
|
|
+--------------------------------+
|
|
|
|
|
|
IBM A2 core
|
|
-----------
|
|
|
|
- Book3E, software loaded TLB + HW loaded indirect TLB entries.
|
|
- 64 bit::
|
|
|
|
+--------------+ +----------------+
|
|
| A2 core | --> | WSP |
|
|
+--------------+ +----------------+
|
|
|
|
|
|
|
|
v
|
|
+--------------+
|
|
| BG/Q |
|
|
+--------------+
|