linux/arch/x86/events
Kan Liang b0560bfd4b perf/x86/intel: Clean up the hybrid CPU type handling code
There is a fairly long list of grievances about the current code. The
main beefs:

   1. hybrid_big_small assumes that the *HARDWARE* (CPUID) provided
      core types are a bitmap. They are not. If Intel happened to
      make a core type of 0xff, hilarity would ensue.
   2. adl_get_hybrid_cpu_type() utterly inscrutable.  There are
      precisely zero comments and zero changelog about what it is
      attempting to do.

According to Kan, the adl_get_hybrid_cpu_type() is there because some
Alder Lake (ADL) CPUs can do some silly things. Some ADL models are
*supposed* to be hybrid CPUs with big and little cores, but there are
some SKUs that only have big cores. CPUID(0x1a) on those CPUs does
not say that the CPUs are big cores. It apparently just returns 0x0.
It confuses perf because it expects to see either 0x40 (Core) or
0x20 (Atom).

The perf workaround for this is to watch for a CPU core saying it is
type 0x0. If that happens on an Alder Lake, it calls
x86_pmu.get_hybrid_cpu_type() and just assumes that the core is a
Core (0x40) CPU.

To fix up the mess, separate out the CPU types and the 'pmu' types.
This allows 'hybrid_pmu_type' bitmaps without worrying that some
future CPU type will set multiple bits.

Since the types are now separate, add a function to glue them back
together again. Actual comment on the situation in the glue
function (find_hybrid_pmu_for_cpu()).

Also, give ->get_hybrid_cpu_type() a real return type and make it
clear that it is overriding the *CPU* type, not the PMU type.

Rename cpu_type to pmu_type in the struct x86_hybrid_pmu to reflect the
change.

Originally-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230829125806.3016082-6-kan.liang@linux.intel.com
2023-08-29 20:59:23 +02:00
..
amd perf/x86/ibs: Set mem_lvl_num, mem_remote and mem_hops for data_src 2023-07-26 12:28:45 +02:00
intel perf/x86/intel: Clean up the hybrid CPU type handling code 2023-08-29 20:59:23 +02:00
zhaoxin x86/perf/zhaoxin: Add stepping check for ZXC 2023-02-11 11:18:12 +01:00
core.c perf/x86/intel: Clean up the hybrid CPU type handling code 2023-08-29 20:59:23 +02:00
Kconfig perf/x86/Kconfig: Fix indentation in the Kconfig file 2022-05-25 15:54:26 +02:00
Makefile perf/x86: Move branch classifier 2022-08-27 00:05:44 +02:00
msr.c x86/cpu: Fix Gracemont uarch 2023-08-09 21:51:06 +02:00
perf_event_flags.h x86/perf: Assert all platform event flags are within PERF_EVENT_FLAG_ARCH 2022-09-07 21:54:01 +02:00
perf_event.h perf/x86/intel: Clean up the hybrid CPU type handling code 2023-08-29 20:59:23 +02:00
probe.c perf/x86/rapl: Add msr mask support 2021-02-10 14:44:54 +01:00
probe.h perf/x86/rapl: Add msr mask support 2021-02-10 14:44:54 +01:00
rapl.c x86/cpu: Fix Gracemont uarch 2023-08-09 21:51:06 +02:00
utils.c perf/x86/utils: Fix uninitialized var in get_branch_type() 2022-09-29 12:20:56 +02:00