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8e9198d069
the definitions can be shared by different IP components. v2: fix include path Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
101 lines
4.6 KiB
C
101 lines
4.6 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Stanislaw Skowronek
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*/
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#ifndef ATOM_NAMES_H
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#define ATOM_NAMES_H
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#include "atom.h"
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#ifdef ATOM_DEBUG
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#define ATOM_OP_NAMES_CNT 123
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static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
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"RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
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"MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
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"OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
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"SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
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"SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
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"SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
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"MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
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"DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
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"ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
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"SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
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"SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
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"COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
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"JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
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"JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
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"TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
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"CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
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"CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
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"MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
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"RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
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"XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
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"SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
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"DEBUG", "CTB_DS",
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};
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#define ATOM_TABLE_NAMES_CNT 74
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static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
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"ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
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"VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
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"GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
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"GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
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"DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
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"MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
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"EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
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"DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
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"DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
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"CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
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"TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
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"EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
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"EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
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"SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
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"EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
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"LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
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"GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
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"DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
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"ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
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"ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
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"MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
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"VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
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"EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
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"CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
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"MemoryDeviceInit", "EnableYUV",
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};
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#define ATOM_IO_NAMES_CNT 5
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static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
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"MM", "PLL", "MC", "PCIE", "PCIE PORT",
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};
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#else
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#define ATOM_OP_NAMES_CNT 0
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#define ATOM_TABLE_NAMES_CNT 0
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#define ATOM_IO_NAMES_CNT 0
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#endif
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#endif
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