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6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
265 lines
6.3 KiB
C
265 lines
6.3 KiB
C
/*
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* linux/arch/alpha/kernel/sys_mikasa.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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*
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* Code supporting the MIKASA (AlphaServer 1000).
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_apecs.h>
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#include <asm/core_cia.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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/* Note mask bit is true for ENABLED irqs. */
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static int cached_irq_mask;
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static inline void
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mikasa_update_irq_hw(int mask)
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{
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outw(mask, 0x536);
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}
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static inline void
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mikasa_enable_irq(unsigned int irq)
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{
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mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
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}
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static void
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mikasa_disable_irq(unsigned int irq)
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{
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mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
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}
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static unsigned int
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mikasa_startup_irq(unsigned int irq)
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{
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mikasa_enable_irq(irq);
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return 0;
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}
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static void
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mikasa_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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mikasa_enable_irq(irq);
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}
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static struct hw_interrupt_type mikasa_irq_type = {
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.typename = "MIKASA",
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.startup = mikasa_startup_irq,
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.shutdown = mikasa_disable_irq,
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.enable = mikasa_enable_irq,
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.disable = mikasa_disable_irq,
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.ack = mikasa_disable_irq,
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.end = mikasa_end_irq,
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};
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static void
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mikasa_device_interrupt(unsigned long vector, struct pt_regs *regs)
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{
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unsigned long pld;
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unsigned int i;
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/* Read the interrupt summary registers */
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pld = (((~inw(0x534) & 0x0000ffffUL) << 16)
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| (((unsigned long) inb(0xa0)) << 8)
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| inb(0x20));
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/*
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* Now for every possible bit set, work through them and call
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* the appropriate interrupt handler.
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*/
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while (pld) {
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i = ffz(~pld);
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pld &= pld - 1; /* clear least bit set */
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if (i < 16) {
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isa_device_interrupt(vector, regs);
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} else {
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handle_irq(i, regs);
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}
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}
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}
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static void __init
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mikasa_init_irq(void)
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{
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long i;
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if (alpha_using_srm)
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alpha_mv.device_interrupt = srm_device_interrupt;
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mikasa_update_irq_hw(0);
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for (i = 16; i < 32; ++i) {
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irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
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irq_desc[i].chip = &mikasa_irq_type;
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}
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init_i8259a_irqs();
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common_init_isa_dma();
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}
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/*
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* PCI Fixup configuration.
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*
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* Summary @ 0x536:
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* Bit Meaning
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* 0 Interrupt Line A from slot 0
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* 1 Interrupt Line B from slot 0
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* 2 Interrupt Line C from slot 0
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* 3 Interrupt Line D from slot 0
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* 4 Interrupt Line A from slot 1
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* 5 Interrupt line B from slot 1
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* 6 Interrupt Line C from slot 1
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* 7 Interrupt Line D from slot 1
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* 8 Interrupt Line A from slot 2
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* 9 Interrupt Line B from slot 2
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*10 Interrupt Line C from slot 2
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*11 Interrupt Line D from slot 2
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*12 NCR 810 SCSI
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*13 Power Supply Fail
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*14 Temperature Warn
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*15 Reserved
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*
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* The device to slot mapping looks like:
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*
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* Slot Device
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* 6 NCR SCSI controller
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* 7 Intel PCI-EISA bridge chip
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* 11 PCI on board slot 0
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* 12 PCI on board slot 1
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* 13 PCI on board slot 2
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*
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*
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* This two layered interrupt approach means that we allocate IRQ 16 and
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* above for PCI interrupts. The IRQ relates to which bit the interrupt
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* comes in on. This makes interrupt processing much easier.
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*/
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static int __init
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mikasa_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[8][5] __initdata = {
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/*INT INTA INTB INTC INTD */
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{16+12, 16+12, 16+12, 16+12, 16+12}, /* IdSel 17, SCSI */
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{ -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
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{ -1, -1, -1, -1, -1}, /* IdSel 19, ???? */
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{ -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
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{ -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
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{ 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 0 */
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{ 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
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{ 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 24, slot 2 */
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};
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const long min_idsel = 6, max_idsel = 13, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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}
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#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
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static void
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mikasa_apecs_machine_check(unsigned long vector, unsigned long la_ptr,
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struct pt_regs * regs)
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{
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#define MCHK_NO_DEVSEL 0x205U
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#define MCHK_NO_TABT 0x204U
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struct el_common *mchk_header;
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unsigned int code;
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mchk_header = (struct el_common *)la_ptr;
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/* Clear the error before any reporting. */
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mb();
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mb(); /* magic */
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draina();
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apecs_pci_clr_err();
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wrmces(0x7);
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mb();
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code = mchk_header->code;
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process_mcheck_info(vector, la_ptr, regs, "MIKASA APECS",
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(mcheck_expected(0)
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&& (code == MCHK_NO_DEVSEL
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|| code == MCHK_NO_TABT)));
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}
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#endif
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/*
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* The System Vector
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*/
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#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
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struct alpha_machine_vector mikasa_mv __initmv = {
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.vector_name = "Mikasa",
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DO_EV4_MMU,
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DO_DEFAULT_RTC,
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DO_APECS_IO,
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.machine_check = mikasa_apecs_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
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.nr_irqs = 32,
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.device_interrupt = mikasa_device_interrupt,
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.init_arch = apecs_init_arch,
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.init_irq = mikasa_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = common_init_pci,
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.pci_map_irq = mikasa_map_irq,
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.pci_swizzle = common_swizzle,
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};
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ALIAS_MV(mikasa)
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#endif
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
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struct alpha_machine_vector mikasa_primo_mv __initmv = {
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.vector_name = "Mikasa-Primo",
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DO_EV5_MMU,
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DO_DEFAULT_RTC,
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DO_CIA_IO,
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.machine_check = cia_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = CIA_DEFAULT_MEM_BASE,
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.nr_irqs = 32,
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.device_interrupt = mikasa_device_interrupt,
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.init_arch = cia_init_arch,
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.init_irq = mikasa_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = cia_init_pci,
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.kill_arch = cia_kill_arch,
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.pci_map_irq = mikasa_map_irq,
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.pci_swizzle = common_swizzle,
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};
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ALIAS_MV(mikasa_primo)
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#endif
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