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c4a11bf423
Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides clock numbers for the ingenic,x1830-cgu DT binding.
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*
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* They are roughly ordered as:
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* - external clocks
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* - PLLs
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* - muxes/dividers in the order they appear in the x1830 programmers manual
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* - gates in order of their bit in the CLKGR* registers
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*/
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#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__
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#define __DT_BINDINGS_CLOCK_X1830_CGU_H__
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#define X1830_CLK_EXCLK 0
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#define X1830_CLK_RTCLK 1
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#define X1830_CLK_APLL 2
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#define X1830_CLK_MPLL 3
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#define X1830_CLK_EPLL 4
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#define X1830_CLK_VPLL 5
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#define X1830_CLK_OTGPHY 6
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#define X1830_CLK_SCLKA 7
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#define X1830_CLK_CPUMUX 8
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#define X1830_CLK_CPU 9
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#define X1830_CLK_L2CACHE 10
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#define X1830_CLK_AHB0 11
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#define X1830_CLK_AHB2PMUX 12
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#define X1830_CLK_AHB2 13
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#define X1830_CLK_PCLK 14
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#define X1830_CLK_DDR 15
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#define X1830_CLK_MAC 16
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#define X1830_CLK_LCD 17
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#define X1830_CLK_MSCMUX 18
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#define X1830_CLK_MSC0 19
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#define X1830_CLK_MSC1 20
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#define X1830_CLK_SSIPLL 21
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#define X1830_CLK_SSIPLL_DIV2 22
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#define X1830_CLK_SSIMUX 23
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#define X1830_CLK_EMC 24
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#define X1830_CLK_EFUSE 25
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#define X1830_CLK_OTG 26
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#define X1830_CLK_SSI0 27
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#define X1830_CLK_SMB0 28
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#define X1830_CLK_SMB1 29
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#define X1830_CLK_SMB2 30
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#define X1830_CLK_UART0 31
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#define X1830_CLK_UART1 32
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#define X1830_CLK_SSI1 33
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#define X1830_CLK_SFC 34
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#define X1830_CLK_PDMA 35
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#define X1830_CLK_TCU 36
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#define X1830_CLK_DTRNG 37
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#define X1830_CLK_OST 38
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#define X1830_CLK_EXCLK_DIV512 39
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#define X1830_CLK_RTC 40
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#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
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