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The call has been assuming all clksrc-clks' divider size is 4 bits, but this may not be the case anymore. Use the reg_div.size parameter to calculate the maximum value it can take and check against that. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
213 lines
4.8 KiB
C
213 lines
4.8 KiB
C
/* linux/arch/arm/plat-samsung/clock-clksrc.c
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*
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/sysdev.h>
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#include <linux/io.h>
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/cpu-freq.h>
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static inline struct clksrc_clk *to_clksrc(struct clk *clk)
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{
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return container_of(clk, struct clksrc_clk, clk);
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}
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static inline u32 bit_mask(u32 shift, u32 nr_bits)
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{
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u32 mask = 0xffffffff >> (32 - nr_bits);
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return mask << shift;
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}
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static unsigned long s3c_getrate_clksrc(struct clk *clk)
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{
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struct clksrc_clk *sclk = to_clksrc(clk);
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unsigned long rate = clk_get_rate(clk->parent);
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u32 clkdiv = __raw_readl(sclk->reg_div.reg);
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u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
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clkdiv &= mask;
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clkdiv >>= sclk->reg_div.shift;
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clkdiv++;
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rate /= clkdiv;
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return rate;
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}
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static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate)
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{
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struct clksrc_clk *sclk = to_clksrc(clk);
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void __iomem *reg = sclk->reg_div.reg;
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unsigned int div;
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u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
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u32 val;
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rate = clk_round_rate(clk, rate);
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div = clk_get_rate(clk->parent) / rate;
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if (div > (1 << sclk->reg_div.size))
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return -EINVAL;
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val = __raw_readl(reg);
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val &= ~mask;
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val |= (div - 1) << sclk->reg_div.shift;
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__raw_writel(val, reg);
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return 0;
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}
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static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent)
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{
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struct clksrc_clk *sclk = to_clksrc(clk);
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struct clksrc_sources *srcs = sclk->sources;
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u32 clksrc = __raw_readl(sclk->reg_src.reg);
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u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size);
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int src_nr = -1;
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int ptr;
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for (ptr = 0; ptr < srcs->nr_sources; ptr++)
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if (srcs->sources[ptr] == parent) {
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src_nr = ptr;
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break;
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}
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if (src_nr >= 0) {
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clk->parent = parent;
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clksrc &= ~mask;
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clksrc |= src_nr << sclk->reg_src.shift;
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__raw_writel(clksrc, sclk->reg_src.reg);
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return 0;
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}
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return -EINVAL;
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}
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static unsigned long s3c_roundrate_clksrc(struct clk *clk,
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unsigned long rate)
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{
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struct clksrc_clk *sclk = to_clksrc(clk);
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unsigned long parent_rate = clk_get_rate(clk->parent);
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int max_div = 1 << sclk->reg_div.size;
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int div;
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if (rate >= parent_rate)
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rate = parent_rate;
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else {
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div = parent_rate / rate;
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if (parent_rate % rate)
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div++;
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if (div == 0)
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div = 1;
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if (div > max_div)
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div = max_div;
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rate = parent_rate / div;
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}
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return rate;
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}
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/* Clock initialisation code */
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void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce)
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{
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struct clksrc_sources *srcs = clk->sources;
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u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size);
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u32 clksrc;
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if (!clk->reg_src.reg) {
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if (!clk->clk.parent)
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printk(KERN_ERR "%s: no parent clock specified\n",
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clk->clk.name);
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return;
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}
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clksrc = __raw_readl(clk->reg_src.reg);
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clksrc &= mask;
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clksrc >>= clk->reg_src.shift;
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if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
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printk(KERN_ERR "%s: bad source %d\n",
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clk->clk.name, clksrc);
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return;
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}
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clk->clk.parent = srcs->sources[clksrc];
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if (announce)
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printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
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clk->clk.name, clk->clk.parent->name, clksrc,
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clk_get_rate(&clk->clk));
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}
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static struct clk_ops clksrc_ops = {
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.set_parent = s3c_setparent_clksrc,
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.get_rate = s3c_getrate_clksrc,
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.set_rate = s3c_setrate_clksrc,
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.round_rate = s3c_roundrate_clksrc,
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};
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static struct clk_ops clksrc_ops_nodiv = {
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.set_parent = s3c_setparent_clksrc,
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};
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static struct clk_ops clksrc_ops_nosrc = {
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.get_rate = s3c_getrate_clksrc,
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.set_rate = s3c_setrate_clksrc,
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.round_rate = s3c_roundrate_clksrc,
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};
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void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size)
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{
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int ret;
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for (; size > 0; size--, clksrc++) {
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if (!clksrc->reg_div.reg && !clksrc->reg_src.reg)
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printk(KERN_ERR "%s: clock %s has no registers set\n",
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__func__, clksrc->clk.name);
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/* fill in the default functions */
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if (!clksrc->clk.ops) {
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if (!clksrc->reg_div.reg)
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clksrc->clk.ops = &clksrc_ops_nodiv;
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else if (!clksrc->reg_src.reg)
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clksrc->clk.ops = &clksrc_ops_nosrc;
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else
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clksrc->clk.ops = &clksrc_ops;
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}
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/* setup the clocksource, but do not announce it
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* as it may be re-set by the setup routines
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* called after the rest of the clocks have been
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* registered
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*/
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s3c_set_clksrc(clksrc, false);
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ret = s3c24xx_register_clock(&clksrc->clk);
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if (ret < 0) {
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printk(KERN_ERR "%s: failed to register %s (%d)\n",
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__func__, clksrc->clk.name, ret);
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}
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}
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}
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