mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-16 00:34:20 +08:00
bb6951b84f
Commit c6c889d932 ("PCI/portdrv: Remove pcie_port_bus_type link order
dependency") removed pcie_port_bus_{,un}register() but erroneously
retained their declarations in portdrv.h. Remove them as well.
Link: https://lore.kernel.org/r/7fd76b0591c37287ab94d911d8fd9ab9a2afcd16.1627638184.git.lukas@wunner.de
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
146 lines
4.4 KiB
C
146 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Purpose: PCI Express Port Bus Driver's Internal Data Structures
|
|
*
|
|
* Copyright (C) 2004 Intel
|
|
* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
|
|
*/
|
|
|
|
#ifndef _PORTDRV_H_
|
|
#define _PORTDRV_H_
|
|
|
|
#include <linux/compiler.h>
|
|
|
|
/* Service Type */
|
|
#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */
|
|
#define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT)
|
|
#define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */
|
|
#define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT)
|
|
#define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */
|
|
#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
|
|
#define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */
|
|
#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
|
|
#define PCIE_PORT_SERVICE_BWNOTIF_SHIFT 4 /* Bandwidth notification */
|
|
#define PCIE_PORT_SERVICE_BWNOTIF (1 << PCIE_PORT_SERVICE_BWNOTIF_SHIFT)
|
|
|
|
#define PCIE_PORT_DEVICE_MAXSERVICES 5
|
|
|
|
extern bool pcie_ports_dpc_native;
|
|
|
|
#ifdef CONFIG_PCIEAER
|
|
int pcie_aer_init(void);
|
|
int pcie_aer_is_native(struct pci_dev *dev);
|
|
#else
|
|
static inline int pcie_aer_init(void) { return 0; }
|
|
static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
|
|
#endif
|
|
|
|
#ifdef CONFIG_HOTPLUG_PCI_PCIE
|
|
int pcie_hp_init(void);
|
|
#else
|
|
static inline int pcie_hp_init(void) { return 0; }
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE_PME
|
|
int pcie_pme_init(void);
|
|
#else
|
|
static inline int pcie_pme_init(void) { return 0; }
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE_DPC
|
|
int pcie_dpc_init(void);
|
|
#else
|
|
static inline int pcie_dpc_init(void) { return 0; }
|
|
#endif
|
|
|
|
/* Port Type */
|
|
#define PCIE_ANY_PORT (~0)
|
|
|
|
struct pcie_device {
|
|
int irq; /* Service IRQ/MSI/MSI-X Vector */
|
|
struct pci_dev *port; /* Root/Upstream/Downstream Port */
|
|
u32 service; /* Port service this device represents */
|
|
void *priv_data; /* Service Private Data */
|
|
struct device device; /* Generic Device Interface */
|
|
};
|
|
#define to_pcie_device(d) container_of(d, struct pcie_device, device)
|
|
|
|
static inline void set_service_data(struct pcie_device *dev, void *data)
|
|
{
|
|
dev->priv_data = data;
|
|
}
|
|
|
|
static inline void *get_service_data(struct pcie_device *dev)
|
|
{
|
|
return dev->priv_data;
|
|
}
|
|
|
|
struct pcie_port_service_driver {
|
|
const char *name;
|
|
int (*probe)(struct pcie_device *dev);
|
|
void (*remove)(struct pcie_device *dev);
|
|
int (*suspend)(struct pcie_device *dev);
|
|
int (*resume_noirq)(struct pcie_device *dev);
|
|
int (*resume)(struct pcie_device *dev);
|
|
int (*runtime_suspend)(struct pcie_device *dev);
|
|
int (*runtime_resume)(struct pcie_device *dev);
|
|
|
|
int (*slot_reset)(struct pcie_device *dev);
|
|
|
|
int port_type; /* Type of the port this driver can handle */
|
|
u32 service; /* Port service this device represents */
|
|
|
|
struct device_driver driver;
|
|
};
|
|
#define to_service_driver(d) \
|
|
container_of(d, struct pcie_port_service_driver, driver)
|
|
|
|
int pcie_port_service_register(struct pcie_port_service_driver *new);
|
|
void pcie_port_service_unregister(struct pcie_port_service_driver *new);
|
|
|
|
/*
|
|
* The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
|
|
* be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI
|
|
* supports a maximum of 32 vectors per function.
|
|
*/
|
|
#define PCIE_PORT_MAX_MSI_ENTRIES 32
|
|
|
|
#define get_descriptor_id(type, service) (((type - 4) << 8) | service)
|
|
|
|
extern struct bus_type pcie_port_bus_type;
|
|
int pcie_port_device_register(struct pci_dev *dev);
|
|
int pcie_port_device_iter(struct device *dev, void *data);
|
|
#ifdef CONFIG_PM
|
|
int pcie_port_device_suspend(struct device *dev);
|
|
int pcie_port_device_resume_noirq(struct device *dev);
|
|
int pcie_port_device_resume(struct device *dev);
|
|
int pcie_port_device_runtime_suspend(struct device *dev);
|
|
int pcie_port_device_runtime_resume(struct device *dev);
|
|
#endif
|
|
void pcie_port_device_remove(struct pci_dev *dev);
|
|
|
|
struct pci_dev;
|
|
|
|
#ifdef CONFIG_PCIE_PME
|
|
extern bool pcie_pme_msi_disabled;
|
|
|
|
static inline void pcie_pme_disable_msi(void)
|
|
{
|
|
pcie_pme_msi_disabled = true;
|
|
}
|
|
|
|
static inline bool pcie_pme_no_msi(void)
|
|
{
|
|
return pcie_pme_msi_disabled;
|
|
}
|
|
|
|
void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable);
|
|
#else /* !CONFIG_PCIE_PME */
|
|
static inline void pcie_pme_disable_msi(void) {}
|
|
static inline bool pcie_pme_no_msi(void) { return false; }
|
|
static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
|
|
#endif /* !CONFIG_PCIE_PME */
|
|
|
|
struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
|
|
#endif /* _PORTDRV_H_ */
|