mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-19 10:14:23 +08:00
5b3b16880f
These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S
86 lines
2.6 KiB
Plaintext
86 lines
2.6 KiB
Plaintext
config CAVIUM_OCTEON_SPECIFIC_OPTIONS
|
|
bool "Enable Octeon specific options"
|
|
depends on CPU_CAVIUM_OCTEON
|
|
default "y"
|
|
|
|
config CAVIUM_OCTEON_2ND_KERNEL
|
|
bool "Build the kernel to be used as a 2nd kernel on the same chip"
|
|
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
|
|
default "n"
|
|
help
|
|
This option configures this kernel to be linked at a different
|
|
address and use the 2nd uart for output. This allows a kernel built
|
|
with this option to be run at the same time as one built without this
|
|
option.
|
|
|
|
config CAVIUM_OCTEON_HW_FIX_UNALIGNED
|
|
bool "Enable hardware fixups of unaligned loads and stores"
|
|
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
|
|
default "y"
|
|
help
|
|
Configure the Octeon hardware to automatically fix unaligned loads
|
|
and stores. Normally unaligned accesses are fixed using a kernel
|
|
exception handler. This option enables the hardware automatic fixups,
|
|
which requires only an extra 3 cycles. Disable this option if you
|
|
are running code that relies on address exceptions on unaligned
|
|
accesses.
|
|
|
|
config CAVIUM_OCTEON_CVMSEG_SIZE
|
|
int "Number of L1 cache lines reserved for CVMSEG memory"
|
|
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
|
|
range 0 54
|
|
default 1
|
|
help
|
|
CVMSEG LM is a segment that accesses portions of the dcache as a
|
|
local memory; the larger CVMSEG is, the smaller the cache is.
|
|
This selects the size of CVMSEG LM, which is in cache blocks. The
|
|
legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
|
|
between zero and 6192 bytes).
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2
|
|
bool "Lock often used kernel code in the L2"
|
|
depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
|
|
default "y"
|
|
help
|
|
Enable locking parts of the kernel into the L2 cache.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_TLB
|
|
bool "Lock the TLB handler in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the low level TLB fast path into L2.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
|
|
bool "Lock the exception handler in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the low level exception handler into L2.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
|
|
bool "Lock the interrupt handler in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the low level interrupt handler into L2.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
|
|
bool "Lock the 2nd level interrupt handler in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the 2nd level interrupt handler in L2.
|
|
|
|
config CAVIUM_OCTEON_LOCK_L2_MEMCPY
|
|
bool "Lock memcpy() in L2"
|
|
depends on CAVIUM_OCTEON_LOCK_L2
|
|
default "y"
|
|
help
|
|
Lock the kernel's implementation of memcpy() into L2.
|
|
|
|
config ARCH_SPARSEMEM_ENABLE
|
|
def_bool y
|
|
select SPARSEMEM_STATIC
|
|
depends on CPU_CAVIUM_OCTEON
|