Palmer Dabbelt 52420e483d RISC-V: Provide the frequency of time CSR via hwprobe ... The RISC-V architecture makes a real time counter CSR (via RDTIME instruction) available for applications in U-mode but there is no architected mechanism for an application to discover the frequency the counter is running at. Some applications (e.g., DPDK) use the time counter for basic performance analysis as well as fine grained time-keeping. Add support to the hwprobe system call to export the time CSR frequency to code running in U-mode. Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> Reviewed-by: Evan Green <evan@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Punit Agrawal <punit.agrawal@bytedance.com> Link: https://lore.kernel.org/r/20240702033731.71955-2-cuiyunhui@bytedance.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-07-26 05:50:51 -07:00
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acpi.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot-image-header.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
boot.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
cmodx.rst	documentation: Fix riscv cmodx example	2024-07-01 10:50:18 -07:00
features.rst	docs: kernel_feat.py: fix potential command injection	2024-01-11 09:21:01 -07:00
hwprobe.rst	RISC-V: Provide the frequency of time CSR via hwprobe	2024-07-26 05:50:51 -07:00
index.rst	documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl	2024-04-18 08:10:59 -07:00
patch-acceptance.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
uabi.rst	Documentation: RISC-V: uabi: Only scalar misaligned loads are supported	2024-05-30 09:42:53 -07:00
vector.rst	docs: move riscv under arch	2023-10-10 13:37:43 -06:00
vm-layout.rst	riscv: Extend sv39 linear mapping max size to 128G	2024-07-26 05:50:50 -07:00