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97f7547103
We rely on probe order of this driver to determine the line number for the uart port. This makes it impossible to know the line number when these devices are populated via DT. Use the DT alias mechanism to assign the line based on the aliases node. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1159 lines
27 KiB
C
1159 lines
27 KiB
C
/*
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* Driver for msm7k serial device and console
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Robert Love <rlove@google.com>
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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# define SUPPORT_SYSRQ
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#endif
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#include <linux/atomic.h>
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#include <linux/hrtimer.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "msm_serial.h"
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enum {
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UARTDM_1P1 = 1,
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UARTDM_1P2,
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UARTDM_1P3,
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UARTDM_1P4,
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};
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struct msm_port {
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struct uart_port uart;
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char name[16];
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struct clk *clk;
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struct clk *pclk;
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unsigned int imr;
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int is_uartdm;
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unsigned int old_snap_state;
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bool break_detected;
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};
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static inline void wait_for_xmitr(struct uart_port *port)
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{
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while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
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if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
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break;
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udelay(1);
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}
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msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
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}
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static void msm_stop_tx(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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msm_port->imr &= ~UART_IMR_TXLEV;
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msm_write(port, msm_port->imr, UART_IMR);
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}
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static void msm_start_tx(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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msm_port->imr |= UART_IMR_TXLEV;
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msm_write(port, msm_port->imr, UART_IMR);
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}
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static void msm_stop_rx(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
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msm_write(port, msm_port->imr, UART_IMR);
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}
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static void msm_enable_ms(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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msm_port->imr |= UART_IMR_DELTA_CTS;
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msm_write(port, msm_port->imr, UART_IMR);
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}
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static void handle_rx_dm(struct uart_port *port, unsigned int misr)
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{
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struct tty_port *tport = &port->state->port;
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unsigned int sr;
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int count = 0;
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struct msm_port *msm_port = UART_TO_MSM(port);
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if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
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port->icount.overrun++;
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tty_insert_flip_char(tport, 0, TTY_OVERRUN);
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msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
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}
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if (misr & UART_IMR_RXSTALE) {
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count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
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msm_port->old_snap_state;
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msm_port->old_snap_state = 0;
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} else {
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count = 4 * (msm_read(port, UART_RFWR));
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msm_port->old_snap_state += count;
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}
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/* TODO: Precise error reporting */
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port->icount.rx += count;
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while (count > 0) {
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unsigned char buf[4];
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int sysrq, r_count, i;
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sr = msm_read(port, UART_SR);
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if ((sr & UART_SR_RX_READY) == 0) {
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msm_port->old_snap_state -= count;
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break;
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}
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ioread32_rep(port->membase + UARTDM_RF, buf, 1);
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r_count = min_t(int, count, sizeof(buf));
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for (i = 0; i < r_count; i++) {
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char flag = TTY_NORMAL;
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if (msm_port->break_detected && buf[i] == 0) {
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port->icount.brk++;
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flag = TTY_BREAK;
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msm_port->break_detected = false;
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if (uart_handle_break(port))
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continue;
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}
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if (!(port->read_status_mask & UART_SR_RX_BREAK))
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flag = TTY_NORMAL;
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spin_unlock(&port->lock);
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sysrq = uart_handle_sysrq_char(port, buf[i]);
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spin_lock(&port->lock);
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if (!sysrq)
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tty_insert_flip_char(tport, buf[i], flag);
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}
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count -= r_count;
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}
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spin_unlock(&port->lock);
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tty_flip_buffer_push(tport);
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spin_lock(&port->lock);
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if (misr & (UART_IMR_RXSTALE))
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msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
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msm_write(port, 0xFFFFFF, UARTDM_DMRX);
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msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
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}
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static void handle_rx(struct uart_port *port)
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{
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struct tty_port *tport = &port->state->port;
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unsigned int sr;
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/*
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* Handle overrun. My understanding of the hardware is that overrun
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* is not tied to the RX buffer, so we handle the case out of band.
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*/
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if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
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port->icount.overrun++;
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tty_insert_flip_char(tport, 0, TTY_OVERRUN);
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msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
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}
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/* and now the main RX loop */
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while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
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unsigned int c;
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char flag = TTY_NORMAL;
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int sysrq;
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c = msm_read(port, UART_RF);
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if (sr & UART_SR_RX_BREAK) {
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port->icount.brk++;
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if (uart_handle_break(port))
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continue;
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} else if (sr & UART_SR_PAR_FRAME_ERR) {
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port->icount.frame++;
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} else {
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port->icount.rx++;
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}
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/* Mask conditions we're ignorning. */
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sr &= port->read_status_mask;
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if (sr & UART_SR_RX_BREAK)
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flag = TTY_BREAK;
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else if (sr & UART_SR_PAR_FRAME_ERR)
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flag = TTY_FRAME;
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spin_unlock(&port->lock);
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sysrq = uart_handle_sysrq_char(port, c);
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spin_lock(&port->lock);
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if (!sysrq)
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tty_insert_flip_char(tport, c, flag);
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}
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spin_unlock(&port->lock);
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tty_flip_buffer_push(tport);
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spin_lock(&port->lock);
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}
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static void reset_dm_count(struct uart_port *port, int count)
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{
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wait_for_xmitr(port);
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msm_write(port, count, UARTDM_NCF_TX);
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msm_read(port, UARTDM_NCF_TX);
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}
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static void handle_tx(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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struct msm_port *msm_port = UART_TO_MSM(port);
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unsigned int tx_count, num_chars;
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unsigned int tf_pointer = 0;
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void __iomem *tf;
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if (msm_port->is_uartdm)
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tf = port->membase + UARTDM_TF;
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else
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tf = port->membase + UART_TF;
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tx_count = uart_circ_chars_pending(xmit);
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tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail,
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port->fifosize);
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if (port->x_char) {
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if (msm_port->is_uartdm)
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reset_dm_count(port, tx_count + 1);
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iowrite8_rep(tf, &port->x_char, 1);
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port->icount.tx++;
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port->x_char = 0;
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} else if (tx_count && msm_port->is_uartdm) {
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reset_dm_count(port, tx_count);
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}
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while (tf_pointer < tx_count) {
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int i;
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char buf[4] = { 0 };
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if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
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break;
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if (msm_port->is_uartdm)
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num_chars = min(tx_count - tf_pointer,
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(unsigned int)sizeof(buf));
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else
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num_chars = 1;
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for (i = 0; i < num_chars; i++) {
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buf[i] = xmit->buf[xmit->tail + i];
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port->icount.tx++;
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}
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iowrite32_rep(tf, buf, 1);
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xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
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tf_pointer += num_chars;
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}
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/* disable tx interrupts if nothing more to send */
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if (uart_circ_empty(xmit))
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msm_stop_tx(port);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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static void handle_delta_cts(struct uart_port *port)
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{
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msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
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port->icount.cts++;
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wake_up_interruptible(&port->state->port.delta_msr_wait);
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}
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static irqreturn_t msm_irq(int irq, void *dev_id)
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{
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struct uart_port *port = dev_id;
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struct msm_port *msm_port = UART_TO_MSM(port);
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unsigned int misr;
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spin_lock(&port->lock);
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misr = msm_read(port, UART_MISR);
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msm_write(port, 0, UART_IMR); /* disable interrupt */
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if (misr & UART_IMR_RXBREAK_START) {
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msm_port->break_detected = true;
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msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
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}
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if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
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if (msm_port->is_uartdm)
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handle_rx_dm(port, misr);
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else
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handle_rx(port);
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}
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if (misr & UART_IMR_TXLEV)
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handle_tx(port);
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if (misr & UART_IMR_DELTA_CTS)
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handle_delta_cts(port);
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msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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}
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static unsigned int msm_tx_empty(struct uart_port *port)
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{
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return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
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}
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static unsigned int msm_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
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}
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static void msm_reset(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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/* reset everything */
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msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
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msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
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msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
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/* Disable DM modes */
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if (msm_port->is_uartdm)
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msm_write(port, 0, UARTDM_DMEN);
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}
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static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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unsigned int mr;
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mr = msm_read(port, UART_MR1);
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if (!(mctrl & TIOCM_RTS)) {
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mr &= ~UART_MR1_RX_RDY_CTL;
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msm_write(port, mr, UART_MR1);
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msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
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} else {
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mr |= UART_MR1_RX_RDY_CTL;
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msm_write(port, mr, UART_MR1);
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}
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}
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static void msm_break_ctl(struct uart_port *port, int break_ctl)
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{
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if (break_ctl)
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msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
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else
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msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
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}
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struct msm_baud_map {
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u16 divisor;
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u8 code;
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u8 rxstale;
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};
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static const struct msm_baud_map *
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msm_find_best_baud(struct uart_port *port, unsigned int baud)
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{
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unsigned int i, divisor;
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const struct msm_baud_map *entry;
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static const struct msm_baud_map table[] = {
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{ 1536, 0x00, 1 },
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{ 768, 0x11, 1 },
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{ 384, 0x22, 1 },
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{ 192, 0x33, 1 },
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{ 96, 0x44, 1 },
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{ 48, 0x55, 1 },
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{ 32, 0x66, 1 },
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{ 24, 0x77, 1 },
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{ 16, 0x88, 1 },
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{ 12, 0x99, 6 },
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{ 8, 0xaa, 6 },
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{ 6, 0xbb, 6 },
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{ 4, 0xcc, 6 },
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{ 3, 0xdd, 8 },
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{ 2, 0xee, 16 },
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{ 1, 0xff, 31 },
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};
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divisor = uart_get_divisor(port, baud);
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for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
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if (entry->divisor <= divisor)
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break;
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return entry; /* Default to smallest divider */
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}
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static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
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{
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unsigned int rxstale, watermark;
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struct msm_port *msm_port = UART_TO_MSM(port);
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const struct msm_baud_map *entry;
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entry = msm_find_best_baud(port, baud);
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msm_write(port, entry->code, UART_CSR);
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/* RX stale watermark */
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rxstale = entry->rxstale;
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watermark = UART_IPR_STALE_LSB & rxstale;
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watermark |= UART_IPR_RXSTALE_LAST;
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watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
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msm_write(port, watermark, UART_IPR);
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/* set RX watermark */
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watermark = (port->fifosize * 3) / 4;
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msm_write(port, watermark, UART_RFWR);
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/* set TX watermark */
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msm_write(port, 10, UART_TFWR);
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msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
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msm_reset(port);
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/* Enable RX and TX */
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msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
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/* turn on RX and CTS interrupts */
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msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
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UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
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msm_write(port, msm_port->imr, UART_IMR);
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if (msm_port->is_uartdm) {
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msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
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msm_write(port, 0xFFFFFF, UARTDM_DMRX);
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msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
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}
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return baud;
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}
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static void msm_init_clock(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
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clk_prepare_enable(msm_port->clk);
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clk_prepare_enable(msm_port->pclk);
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msm_serial_set_mnd_regs(port);
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}
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static int msm_startup(struct uart_port *port)
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{
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struct msm_port *msm_port = UART_TO_MSM(port);
|
|
unsigned int data, rfr_level;
|
|
int ret;
|
|
|
|
snprintf(msm_port->name, sizeof(msm_port->name),
|
|
"msm_serial%d", port->line);
|
|
|
|
ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
|
|
msm_port->name, port);
|
|
if (unlikely(ret))
|
|
return ret;
|
|
|
|
msm_init_clock(port);
|
|
|
|
if (likely(port->fifosize > 12))
|
|
rfr_level = port->fifosize - 12;
|
|
else
|
|
rfr_level = port->fifosize;
|
|
|
|
/* set automatic RFR level */
|
|
data = msm_read(port, UART_MR1);
|
|
data &= ~UART_MR1_AUTO_RFR_LEVEL1;
|
|
data &= ~UART_MR1_AUTO_RFR_LEVEL0;
|
|
data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
|
|
data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
|
|
msm_write(port, data, UART_MR1);
|
|
return 0;
|
|
}
|
|
|
|
static void msm_shutdown(struct uart_port *port)
|
|
{
|
|
struct msm_port *msm_port = UART_TO_MSM(port);
|
|
|
|
msm_port->imr = 0;
|
|
msm_write(port, 0, UART_IMR); /* disable interrupts */
|
|
|
|
clk_disable_unprepare(msm_port->clk);
|
|
|
|
free_irq(port->irq, port);
|
|
}
|
|
|
|
static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
|
|
struct ktermios *old)
|
|
{
|
|
unsigned long flags;
|
|
unsigned int baud, mr;
|
|
|
|
spin_lock_irqsave(&port->lock, flags);
|
|
|
|
/* calculate and set baud rate */
|
|
baud = uart_get_baud_rate(port, termios, old, 300, 115200);
|
|
baud = msm_set_baud_rate(port, baud);
|
|
if (tty_termios_baud_rate(termios))
|
|
tty_termios_encode_baud_rate(termios, baud, baud);
|
|
|
|
/* calculate parity */
|
|
mr = msm_read(port, UART_MR2);
|
|
mr &= ~UART_MR2_PARITY_MODE;
|
|
if (termios->c_cflag & PARENB) {
|
|
if (termios->c_cflag & PARODD)
|
|
mr |= UART_MR2_PARITY_MODE_ODD;
|
|
else if (termios->c_cflag & CMSPAR)
|
|
mr |= UART_MR2_PARITY_MODE_SPACE;
|
|
else
|
|
mr |= UART_MR2_PARITY_MODE_EVEN;
|
|
}
|
|
|
|
/* calculate bits per char */
|
|
mr &= ~UART_MR2_BITS_PER_CHAR;
|
|
switch (termios->c_cflag & CSIZE) {
|
|
case CS5:
|
|
mr |= UART_MR2_BITS_PER_CHAR_5;
|
|
break;
|
|
case CS6:
|
|
mr |= UART_MR2_BITS_PER_CHAR_6;
|
|
break;
|
|
case CS7:
|
|
mr |= UART_MR2_BITS_PER_CHAR_7;
|
|
break;
|
|
case CS8:
|
|
default:
|
|
mr |= UART_MR2_BITS_PER_CHAR_8;
|
|
break;
|
|
}
|
|
|
|
/* calculate stop bits */
|
|
mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
|
|
if (termios->c_cflag & CSTOPB)
|
|
mr |= UART_MR2_STOP_BIT_LEN_TWO;
|
|
else
|
|
mr |= UART_MR2_STOP_BIT_LEN_ONE;
|
|
|
|
/* set parity, bits per char, and stop bit */
|
|
msm_write(port, mr, UART_MR2);
|
|
|
|
/* calculate and set hardware flow control */
|
|
mr = msm_read(port, UART_MR1);
|
|
mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
|
|
if (termios->c_cflag & CRTSCTS) {
|
|
mr |= UART_MR1_CTS_CTL;
|
|
mr |= UART_MR1_RX_RDY_CTL;
|
|
}
|
|
msm_write(port, mr, UART_MR1);
|
|
|
|
/* Configure status bits to ignore based on termio flags. */
|
|
port->read_status_mask = 0;
|
|
if (termios->c_iflag & INPCK)
|
|
port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
|
|
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
|
|
port->read_status_mask |= UART_SR_RX_BREAK;
|
|
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
|
|
spin_unlock_irqrestore(&port->lock, flags);
|
|
}
|
|
|
|
static const char *msm_type(struct uart_port *port)
|
|
{
|
|
return "MSM";
|
|
}
|
|
|
|
static void msm_release_port(struct uart_port *port)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(port->dev);
|
|
struct resource *uart_resource;
|
|
resource_size_t size;
|
|
|
|
uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (unlikely(!uart_resource))
|
|
return;
|
|
size = resource_size(uart_resource);
|
|
|
|
release_mem_region(port->mapbase, size);
|
|
iounmap(port->membase);
|
|
port->membase = NULL;
|
|
}
|
|
|
|
static int msm_request_port(struct uart_port *port)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(port->dev);
|
|
struct resource *uart_resource;
|
|
resource_size_t size;
|
|
int ret;
|
|
|
|
uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (unlikely(!uart_resource))
|
|
return -ENXIO;
|
|
|
|
size = resource_size(uart_resource);
|
|
|
|
if (!request_mem_region(port->mapbase, size, "msm_serial"))
|
|
return -EBUSY;
|
|
|
|
port->membase = ioremap(port->mapbase, size);
|
|
if (!port->membase) {
|
|
ret = -EBUSY;
|
|
goto fail_release_port;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail_release_port:
|
|
release_mem_region(port->mapbase, size);
|
|
return ret;
|
|
}
|
|
|
|
static void msm_config_port(struct uart_port *port, int flags)
|
|
{
|
|
int ret;
|
|
|
|
if (flags & UART_CONFIG_TYPE) {
|
|
port->type = PORT_MSM;
|
|
ret = msm_request_port(port);
|
|
if (ret)
|
|
return;
|
|
}
|
|
}
|
|
|
|
static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
{
|
|
if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
|
|
return -EINVAL;
|
|
if (unlikely(port->irq != ser->irq))
|
|
return -EINVAL;
|
|
return 0;
|
|
}
|
|
|
|
static void msm_power(struct uart_port *port, unsigned int state,
|
|
unsigned int oldstate)
|
|
{
|
|
struct msm_port *msm_port = UART_TO_MSM(port);
|
|
|
|
switch (state) {
|
|
case 0:
|
|
clk_prepare_enable(msm_port->clk);
|
|
clk_prepare_enable(msm_port->pclk);
|
|
break;
|
|
case 3:
|
|
clk_disable_unprepare(msm_port->clk);
|
|
clk_disable_unprepare(msm_port->pclk);
|
|
break;
|
|
default:
|
|
pr_err("msm_serial: Unknown PM state %d\n", state);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_CONSOLE_POLL
|
|
static int msm_poll_get_char_single(struct uart_port *port)
|
|
{
|
|
struct msm_port *msm_port = UART_TO_MSM(port);
|
|
unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
|
|
|
|
if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
|
|
return NO_POLL_CHAR;
|
|
|
|
return msm_read(port, rf_reg) & 0xff;
|
|
}
|
|
|
|
static int msm_poll_get_char_dm(struct uart_port *port)
|
|
{
|
|
int c;
|
|
static u32 slop;
|
|
static int count;
|
|
unsigned char *sp = (unsigned char *)&slop;
|
|
|
|
/* Check if a previous read had more than one char */
|
|
if (count) {
|
|
c = sp[sizeof(slop) - count];
|
|
count--;
|
|
/* Or if FIFO is empty */
|
|
} else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
|
|
/*
|
|
* If RX packing buffer has less than a word, force stale to
|
|
* push contents into RX FIFO
|
|
*/
|
|
count = msm_read(port, UARTDM_RXFS);
|
|
count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
|
|
if (count) {
|
|
msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
|
|
slop = msm_read(port, UARTDM_RF);
|
|
c = sp[0];
|
|
count--;
|
|
msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
|
|
msm_write(port, 0xFFFFFF, UARTDM_DMRX);
|
|
msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
|
|
UART_CR);
|
|
} else {
|
|
c = NO_POLL_CHAR;
|
|
}
|
|
/* FIFO has a word */
|
|
} else {
|
|
slop = msm_read(port, UARTDM_RF);
|
|
c = sp[0];
|
|
count = sizeof(slop) - 1;
|
|
}
|
|
|
|
return c;
|
|
}
|
|
|
|
static int msm_poll_get_char(struct uart_port *port)
|
|
{
|
|
u32 imr;
|
|
int c;
|
|
struct msm_port *msm_port = UART_TO_MSM(port);
|
|
|
|
/* Disable all interrupts */
|
|
imr = msm_read(port, UART_IMR);
|
|
msm_write(port, 0, UART_IMR);
|
|
|
|
if (msm_port->is_uartdm)
|
|
c = msm_poll_get_char_dm(port);
|
|
else
|
|
c = msm_poll_get_char_single(port);
|
|
|
|
/* Enable interrupts */
|
|
msm_write(port, imr, UART_IMR);
|
|
|
|
return c;
|
|
}
|
|
|
|
static void msm_poll_put_char(struct uart_port *port, unsigned char c)
|
|
{
|
|
u32 imr;
|
|
struct msm_port *msm_port = UART_TO_MSM(port);
|
|
|
|
/* Disable all interrupts */
|
|
imr = msm_read(port, UART_IMR);
|
|
msm_write(port, 0, UART_IMR);
|
|
|
|
if (msm_port->is_uartdm)
|
|
reset_dm_count(port, 1);
|
|
|
|
/* Wait until FIFO is empty */
|
|
while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
|
|
cpu_relax();
|
|
|
|
/* Write a character */
|
|
msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
|
|
|
|
/* Wait until FIFO is empty */
|
|
while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
|
|
cpu_relax();
|
|
|
|
/* Enable interrupts */
|
|
msm_write(port, imr, UART_IMR);
|
|
}
|
|
#endif
|
|
|
|
static struct uart_ops msm_uart_pops = {
|
|
.tx_empty = msm_tx_empty,
|
|
.set_mctrl = msm_set_mctrl,
|
|
.get_mctrl = msm_get_mctrl,
|
|
.stop_tx = msm_stop_tx,
|
|
.start_tx = msm_start_tx,
|
|
.stop_rx = msm_stop_rx,
|
|
.enable_ms = msm_enable_ms,
|
|
.break_ctl = msm_break_ctl,
|
|
.startup = msm_startup,
|
|
.shutdown = msm_shutdown,
|
|
.set_termios = msm_set_termios,
|
|
.type = msm_type,
|
|
.release_port = msm_release_port,
|
|
.request_port = msm_request_port,
|
|
.config_port = msm_config_port,
|
|
.verify_port = msm_verify_port,
|
|
.pm = msm_power,
|
|
#ifdef CONFIG_CONSOLE_POLL
|
|
.poll_get_char = msm_poll_get_char,
|
|
.poll_put_char = msm_poll_put_char,
|
|
#endif
|
|
};
|
|
|
|
static struct msm_port msm_uart_ports[] = {
|
|
{
|
|
.uart = {
|
|
.iotype = UPIO_MEM,
|
|
.ops = &msm_uart_pops,
|
|
.flags = UPF_BOOT_AUTOCONF,
|
|
.fifosize = 64,
|
|
.line = 0,
|
|
},
|
|
},
|
|
{
|
|
.uart = {
|
|
.iotype = UPIO_MEM,
|
|
.ops = &msm_uart_pops,
|
|
.flags = UPF_BOOT_AUTOCONF,
|
|
.fifosize = 64,
|
|
.line = 1,
|
|
},
|
|
},
|
|
{
|
|
.uart = {
|
|
.iotype = UPIO_MEM,
|
|
.ops = &msm_uart_pops,
|
|
.flags = UPF_BOOT_AUTOCONF,
|
|
.fifosize = 64,
|
|
.line = 2,
|
|
},
|
|
},
|
|
};
|
|
|
|
#define UART_NR ARRAY_SIZE(msm_uart_ports)
|
|
|
|
static inline struct uart_port *get_port_from_line(unsigned int line)
|
|
{
|
|
return &msm_uart_ports[line].uart;
|
|
}
|
|
|
|
#ifdef CONFIG_SERIAL_MSM_CONSOLE
|
|
static void __msm_console_write(struct uart_port *port, const char *s,
|
|
unsigned int count, bool is_uartdm)
|
|
{
|
|
int i;
|
|
int num_newlines = 0;
|
|
bool replaced = false;
|
|
void __iomem *tf;
|
|
|
|
if (is_uartdm)
|
|
tf = port->membase + UARTDM_TF;
|
|
else
|
|
tf = port->membase + UART_TF;
|
|
|
|
/* Account for newlines that will get a carriage return added */
|
|
for (i = 0; i < count; i++)
|
|
if (s[i] == '\n')
|
|
num_newlines++;
|
|
count += num_newlines;
|
|
|
|
spin_lock(&port->lock);
|
|
if (is_uartdm)
|
|
reset_dm_count(port, count);
|
|
|
|
i = 0;
|
|
while (i < count) {
|
|
int j;
|
|
unsigned int num_chars;
|
|
char buf[4] = { 0 };
|
|
|
|
if (is_uartdm)
|
|
num_chars = min(count - i, (unsigned int)sizeof(buf));
|
|
else
|
|
num_chars = 1;
|
|
|
|
for (j = 0; j < num_chars; j++) {
|
|
char c = *s;
|
|
|
|
if (c == '\n' && !replaced) {
|
|
buf[j] = '\r';
|
|
j++;
|
|
replaced = true;
|
|
}
|
|
if (j < num_chars) {
|
|
buf[j] = c;
|
|
s++;
|
|
replaced = false;
|
|
}
|
|
}
|
|
|
|
while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
|
|
cpu_relax();
|
|
|
|
iowrite32_rep(tf, buf, 1);
|
|
i += num_chars;
|
|
}
|
|
spin_unlock(&port->lock);
|
|
}
|
|
|
|
static void msm_console_write(struct console *co, const char *s,
|
|
unsigned int count)
|
|
{
|
|
struct uart_port *port;
|
|
struct msm_port *msm_port;
|
|
|
|
BUG_ON(co->index < 0 || co->index >= UART_NR);
|
|
|
|
port = get_port_from_line(co->index);
|
|
msm_port = UART_TO_MSM(port);
|
|
|
|
__msm_console_write(port, s, count, msm_port->is_uartdm);
|
|
}
|
|
|
|
static int __init msm_console_setup(struct console *co, char *options)
|
|
{
|
|
struct uart_port *port;
|
|
struct msm_port *msm_port;
|
|
int baud = 0, flow, bits, parity;
|
|
|
|
if (unlikely(co->index >= UART_NR || co->index < 0))
|
|
return -ENXIO;
|
|
|
|
port = get_port_from_line(co->index);
|
|
msm_port = UART_TO_MSM(port);
|
|
|
|
if (unlikely(!port->membase))
|
|
return -ENXIO;
|
|
|
|
msm_init_clock(port);
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
bits = 8;
|
|
parity = 'n';
|
|
flow = 'n';
|
|
msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
|
|
UART_MR2); /* 8N1 */
|
|
|
|
if (baud < 300 || baud > 115200)
|
|
baud = 115200;
|
|
msm_set_baud_rate(port, baud);
|
|
|
|
msm_reset(port);
|
|
|
|
if (msm_port->is_uartdm) {
|
|
msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
|
|
msm_write(port, UART_CR_TX_ENABLE, UART_CR);
|
|
}
|
|
|
|
pr_info("msm_serial: console setup on port #%d\n", port->line);
|
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static void
|
|
msm_serial_early_write(struct console *con, const char *s, unsigned n)
|
|
{
|
|
struct earlycon_device *dev = con->data;
|
|
|
|
__msm_console_write(&dev->port, s, n, false);
|
|
}
|
|
|
|
static int __init
|
|
msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
|
|
{
|
|
if (!device->port.membase)
|
|
return -ENODEV;
|
|
|
|
device->con->write = msm_serial_early_write;
|
|
return 0;
|
|
}
|
|
EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup);
|
|
OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
|
|
msm_serial_early_console_setup);
|
|
|
|
static void
|
|
msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
|
|
{
|
|
struct earlycon_device *dev = con->data;
|
|
|
|
__msm_console_write(&dev->port, s, n, true);
|
|
}
|
|
|
|
static int __init
|
|
msm_serial_early_console_setup_dm(struct earlycon_device *device,
|
|
const char *opt)
|
|
{
|
|
if (!device->port.membase)
|
|
return -ENODEV;
|
|
|
|
device->con->write = msm_serial_early_write_dm;
|
|
return 0;
|
|
}
|
|
EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm);
|
|
OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
|
|
msm_serial_early_console_setup_dm);
|
|
|
|
static struct uart_driver msm_uart_driver;
|
|
|
|
static struct console msm_console = {
|
|
.name = "ttyMSM",
|
|
.write = msm_console_write,
|
|
.device = uart_console_device,
|
|
.setup = msm_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &msm_uart_driver,
|
|
};
|
|
|
|
#define MSM_CONSOLE (&msm_console)
|
|
|
|
#else
|
|
#define MSM_CONSOLE NULL
|
|
#endif
|
|
|
|
static struct uart_driver msm_uart_driver = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "msm_serial",
|
|
.dev_name = "ttyMSM",
|
|
.nr = UART_NR,
|
|
.cons = MSM_CONSOLE,
|
|
};
|
|
|
|
static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
|
|
|
|
static const struct of_device_id msm_uartdm_table[] = {
|
|
{ .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
|
|
{ .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
|
|
{ .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
|
|
{ .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
|
|
{ }
|
|
};
|
|
|
|
static int msm_serial_probe(struct platform_device *pdev)
|
|
{
|
|
struct msm_port *msm_port;
|
|
struct resource *resource;
|
|
struct uart_port *port;
|
|
const struct of_device_id *id;
|
|
int irq, line;
|
|
|
|
if (pdev->id == -1)
|
|
pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
|
|
|
|
if (pdev->dev.of_node)
|
|
line = of_alias_get_id(pdev->dev.of_node, "serial");
|
|
else
|
|
line = pdev->id;
|
|
|
|
if (unlikely(line < 0 || line >= UART_NR))
|
|
return -ENXIO;
|
|
|
|
dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
|
|
|
|
port = get_port_from_line(line);
|
|
port->dev = &pdev->dev;
|
|
msm_port = UART_TO_MSM(port);
|
|
|
|
id = of_match_device(msm_uartdm_table, &pdev->dev);
|
|
if (id)
|
|
msm_port->is_uartdm = (unsigned long)id->data;
|
|
else
|
|
msm_port->is_uartdm = 0;
|
|
|
|
msm_port->clk = devm_clk_get(&pdev->dev, "core");
|
|
if (IS_ERR(msm_port->clk))
|
|
return PTR_ERR(msm_port->clk);
|
|
|
|
if (msm_port->is_uartdm) {
|
|
msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
|
|
if (IS_ERR(msm_port->pclk))
|
|
return PTR_ERR(msm_port->pclk);
|
|
|
|
clk_set_rate(msm_port->clk, 1843200);
|
|
}
|
|
|
|
port->uartclk = clk_get_rate(msm_port->clk);
|
|
dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
|
|
|
|
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (unlikely(!resource))
|
|
return -ENXIO;
|
|
port->mapbase = resource->start;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (unlikely(irq < 0))
|
|
return -ENXIO;
|
|
port->irq = irq;
|
|
|
|
platform_set_drvdata(pdev, port);
|
|
|
|
return uart_add_one_port(&msm_uart_driver, port);
|
|
}
|
|
|
|
static int msm_serial_remove(struct platform_device *pdev)
|
|
{
|
|
struct uart_port *port = platform_get_drvdata(pdev);
|
|
|
|
uart_remove_one_port(&msm_uart_driver, port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id msm_match_table[] = {
|
|
{ .compatible = "qcom,msm-uart" },
|
|
{ .compatible = "qcom,msm-uartdm" },
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver msm_platform_driver = {
|
|
.remove = msm_serial_remove,
|
|
.probe = msm_serial_probe,
|
|
.driver = {
|
|
.name = "msm_serial",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = msm_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init msm_serial_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = uart_register_driver(&msm_uart_driver);
|
|
if (unlikely(ret))
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&msm_platform_driver);
|
|
if (unlikely(ret))
|
|
uart_unregister_driver(&msm_uart_driver);
|
|
|
|
pr_info("msm_serial: driver initialized\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit msm_serial_exit(void)
|
|
{
|
|
#ifdef CONFIG_SERIAL_MSM_CONSOLE
|
|
unregister_console(&msm_console);
|
|
#endif
|
|
platform_driver_unregister(&msm_platform_driver);
|
|
uart_unregister_driver(&msm_uart_driver);
|
|
}
|
|
|
|
module_init(msm_serial_init);
|
|
module_exit(msm_serial_exit);
|
|
|
|
MODULE_AUTHOR("Robert Love <rlove@google.com>");
|
|
MODULE_DESCRIPTION("Driver for msm7x serial device");
|
|
MODULE_LICENSE("GPL");
|