mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-28 21:45:01 +08:00
dccfd1e439
Device tree and bindings updates for 3.12.
General additions of various on-chip and on-board peripherals on various
platforms as support gets added. Some of the bigger changes are:
- Addition of (new) PCI-e support on Tegra.
- More Tegra4 support, including PMC configuration for Dalmore.
- Addition of a new board for Exynos4 (trats2) and more bindings for 4x12 IP.
- Addition of Allwinner A20 and A31 SoC and board files.
- Move of the ST Ericsson device tree files to now use ste-* prefix.
- More move of hardware description of shmobile platforms to DT.
- Two new board dts files for Freescale MXs.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSKhJrAAoJEIwa5zzehBx3O6YP/AzskDtXdgdaopgZXVQxCIhE
svby8xG2pcFvuAYEv7KNwgk02oC+B5JrUj7ZG42IOPeVo4HN7k80ehxmP5MZwnqs
LpvBRXqUGAzEoJRhCD/lF4tuw+J5R/XgVWkIVz4nQ8tLdsSWJ3QY5LSS6ePTP6Qi
2B3AbeW/7DSada7lHJE9CqIX5xienLo4YgfCWXHNT8ouFGfqKjBxqIbCFyvzrGfs
jSsIsqy1IO0hnk61yHtbPCRl9FJg2rbVwqHBZvKHMW0ls19Q42chlK/dPO5JCb4w
VWMqbdOr8fnbqzicVqUPbShYZjgEd5I6PUgZMXJqEacgX9dj3SfOOtcR9kfrntHE
of7Wi3FzVzWTzclRnub9nHrBIwvThAr+WX+mvbZrD+tuQte8qkFZXO9mw5/hRA7M
K1O1HgaH1R1Xcdo69EWx9o94NYJ9Vs9F6wmS2+nb1B8u83Ee2Uq0GES5oyYqhU56
qg8FOMYUBDwXlHpjt1qiSwAYrabdCyxMx8lt351bxmiyKRFx0hmyGsv6HvlHJ7Oz
hn6xHcNyIoCIuOvWxiLmKKU2ameDn16uSd71MSwomnQ+U4V+QzoqQ4QDgYD6Sgd5
5fln3OYV3JniWeYFw9DkSLKQTYBodz06wA+XOurcNWs3Ls0E9GilKFixKC6GoEVC
uIywadgelMfDux8GGD3x
=1GuI
-----END PGP SIGNATURE-----
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"Device tree and bindings updates for 3.12.
General additions of various on-chip and on-board peripherals on
various platforms as support gets added. Some of the bigger changes
are:
- Addition of (new) PCI-e support on Tegra.
- More Tegra4 support, including PMC configuration for Dalmore.
- Addition of a new board for Exynos4 (trats2) and more bindings for
4x12 IP.
- Addition of Allwinner A20 and A31 SoC and board files.
- Move of the ST Ericsson device tree files to now use ste-* prefix.
- More move of hardware description of shmobile platforms to DT.
- Two new board dts files for Freescale MXs"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (177 commits)
dts: Rename DW APB timer compatible strings
dts: Deprecate ALTR as a vendor prefix
of: add vendor prefix for Altera Corp.
ARM: at91/dt: sam9x5ek: add sound configuration
ARM: at91/dt: sam9x5ek: enable SSC
ARM: at91/dt: sam9x5ek: add WM8731 codec
ARM: at91/dt: sam9x5: add SSC DMA parameters
ARM: at91/dt: add at91rm9200 PQFP package version
ARM: at91: at91rm9200: set default mmc0 pinctrl-names
ARM: at91: at91sam9n12: correct pin number of gpio-key
ARM: at91: at91sam9n12: add qt1070 support
ARM: at91: at91sam9n12: add pinctrl of TWI
ARM: at91: Add PMU support for sama5d3
ARM: at91: at91sam9260: add missing pinctrl-names on mmc
ARM: tegra: configure power off for Dalmore
ARM: DT: binding fixup to align with vendor-prefixes.txt (DT)
ARM: dts: add sdio blocks to bcm28155-ap board
ARM: dts: align sdio numbers to HW definition
ARM: sun7i: Add Olimex A20-Olinuxino-Micro support
ARM: sun7i: Add Allwinner A20 DTSI
...
650 lines
17 KiB
Plaintext
650 lines
17 KiB
Plaintext
#include <dt-bindings/clock/tegra20-car.h>
|
|
#include <dt-bindings/gpio/tegra-gpio.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
#include "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "nvidia,tegra20";
|
|
interrupt-parent = <&intc>;
|
|
|
|
aliases {
|
|
serial0 = &uarta;
|
|
serial1 = &uartb;
|
|
serial2 = &uartc;
|
|
serial3 = &uartd;
|
|
serial4 = &uarte;
|
|
};
|
|
|
|
host1x {
|
|
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
|
reg = <0x50000000 0x00024000>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
|
|
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0x54000000 0x54000000 0x04000000>;
|
|
|
|
mpe {
|
|
compatible = "nvidia,tegra20-mpe";
|
|
reg = <0x54040000 0x00040000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_MPE>;
|
|
};
|
|
|
|
vi {
|
|
compatible = "nvidia,tegra20-vi";
|
|
reg = <0x54080000 0x00040000>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_VI>;
|
|
};
|
|
|
|
epp {
|
|
compatible = "nvidia,tegra20-epp";
|
|
reg = <0x540c0000 0x00040000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_EPP>;
|
|
};
|
|
|
|
isp {
|
|
compatible = "nvidia,tegra20-isp";
|
|
reg = <0x54100000 0x00040000>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_ISP>;
|
|
};
|
|
|
|
gr2d {
|
|
compatible = "nvidia,tegra20-gr2d";
|
|
reg = <0x54140000 0x00040000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
|
|
};
|
|
|
|
gr3d {
|
|
compatible = "nvidia,tegra20-gr3d";
|
|
reg = <0x54180000 0x00040000>;
|
|
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
|
|
};
|
|
|
|
dc@54200000 {
|
|
compatible = "nvidia,tegra20-dc";
|
|
reg = <0x54200000 0x00040000>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_DISP1>,
|
|
<&tegra_car TEGRA20_CLK_PLL_P>;
|
|
clock-names = "disp1", "parent";
|
|
|
|
rgb {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dc@54240000 {
|
|
compatible = "nvidia,tegra20-dc";
|
|
reg = <0x54240000 0x00040000>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_DISP2>,
|
|
<&tegra_car TEGRA20_CLK_PLL_P>;
|
|
clock-names = "disp2", "parent";
|
|
|
|
rgb {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
hdmi {
|
|
compatible = "nvidia,tegra20-hdmi";
|
|
reg = <0x54280000 0x00040000>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_HDMI>,
|
|
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
|
|
clock-names = "hdmi", "parent";
|
|
status = "disabled";
|
|
};
|
|
|
|
tvo {
|
|
compatible = "nvidia,tegra20-tvo";
|
|
reg = <0x542c0000 0x00040000>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_TVO>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dsi {
|
|
compatible = "nvidia,tegra20-dsi";
|
|
reg = <0x54300000 0x00040000>;
|
|
clocks = <&tegra_car TEGRA20_CLK_DSI>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer@50004600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x50040600 0x20>;
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&tegra_car TEGRA20_CLK_TWD>;
|
|
};
|
|
|
|
intc: interrupt-controller {
|
|
compatible = "arm,cortex-a9-gic";
|
|
reg = <0x50041000 0x1000
|
|
0x50040100 0x0100>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
cache-controller {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0x50043000 0x1000>;
|
|
arm,data-latency = <5 5 2>;
|
|
arm,tag-latency = <4 4 2>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
|
|
timer@60005000 {
|
|
compatible = "nvidia,tegra20-timer";
|
|
reg = <0x60005000 0x60>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_TIMER>;
|
|
};
|
|
|
|
tegra_car: clock {
|
|
compatible = "nvidia,tegra20-car";
|
|
reg = <0x60006000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apbdma: dma {
|
|
compatible = "nvidia,tegra20-apbdma";
|
|
reg = <0x6000a000 0x1200>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
|
|
};
|
|
|
|
ahb {
|
|
compatible = "nvidia,tegra20-ahb";
|
|
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
|
|
};
|
|
|
|
gpio: gpio {
|
|
compatible = "nvidia,tegra20-gpio";
|
|
reg = <0x6000d000 0x1000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
pinmux: pinmux {
|
|
compatible = "nvidia,tegra20-pinmux";
|
|
reg = <0x70000014 0x10 /* Tri-state registers */
|
|
0x70000080 0x20 /* Mux registers */
|
|
0x700000a0 0x14 /* Pull-up/down registers */
|
|
0x70000868 0xa8>; /* Pad control registers */
|
|
};
|
|
|
|
das {
|
|
compatible = "nvidia,tegra20-das";
|
|
reg = <0x70000c00 0x80>;
|
|
};
|
|
|
|
tegra_ac97: ac97 {
|
|
compatible = "nvidia,tegra20-ac97";
|
|
reg = <0x70002000 0x200>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 12>;
|
|
clocks = <&tegra_car TEGRA20_CLK_AC97>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s1: i2s@70002800 {
|
|
compatible = "nvidia,tegra20-i2s";
|
|
reg = <0x70002800 0x200>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 2>;
|
|
clocks = <&tegra_car TEGRA20_CLK_I2S1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tegra_i2s2: i2s@70002a00 {
|
|
compatible = "nvidia,tegra20-i2s";
|
|
reg = <0x70002a00 0x200>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 1>;
|
|
clocks = <&tegra_car TEGRA20_CLK_I2S2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/*
|
|
* There are two serial driver i.e. 8250 based simple serial
|
|
* driver and APB DMA based serial driver for higher baudrate
|
|
* and performace. To enable the 8250 based driver, the compatible
|
|
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
|
|
* driver, the comptible is "nvidia,tegra20-hsuart".
|
|
*/
|
|
uarta: serial@70006000 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 8>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTA>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uartb: serial@70006040 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006040 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 9>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTB>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uartc: serial@70006200 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006200 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 10>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTC>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uartd: serial@70006300 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006300 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 19>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTD>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uarte: serial@70006400 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006400 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 20>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTE>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm {
|
|
compatible = "nvidia,tegra20-pwm";
|
|
reg = <0x7000a000 0x100>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&tegra_car TEGRA20_CLK_PWM>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc {
|
|
compatible = "nvidia,tegra20-rtc";
|
|
reg = <0x7000e000 0x100>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_RTC>;
|
|
};
|
|
|
|
i2c@7000c000 {
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000c000 0x100>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_I2C1>,
|
|
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000c380 {
|
|
compatible = "nvidia,tegra20-sflash";
|
|
reg = <0x7000c380 0x80>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 11>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SPI>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000c400 0x100>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_I2C2>,
|
|
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000c500 {
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000c500 0x100>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_I2C3>,
|
|
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
compatible = "nvidia,tegra20-i2c-dvc";
|
|
reg = <0x7000d000 0x200>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_DVC>,
|
|
<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
|
|
clock-names = "div-clk", "fast-clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d400 {
|
|
compatible = "nvidia,tegra20-slink";
|
|
reg = <0x7000d400 0x200>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 15>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SBC1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d600 {
|
|
compatible = "nvidia,tegra20-slink";
|
|
reg = <0x7000d600 0x200>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SBC2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000d800 {
|
|
compatible = "nvidia,tegra20-slink";
|
|
reg = <0x7000d800 0x200>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 17>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SBC3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@7000da00 {
|
|
compatible = "nvidia,tegra20-slink";
|
|
reg = <0x7000da00 0x200>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
nvidia,dma-request-selector = <&apbdma 18>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SBC4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
kbc {
|
|
compatible = "nvidia,tegra20-kbc";
|
|
reg = <0x7000e200 0x100>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_KBC>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmc {
|
|
compatible = "nvidia,tegra20-pmc";
|
|
reg = <0x7000e400 0x400>;
|
|
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
|
|
clock-names = "pclk", "clk32k_in";
|
|
};
|
|
|
|
memory-controller@7000f000 {
|
|
compatible = "nvidia,tegra20-mc";
|
|
reg = <0x7000f000 0x024
|
|
0x7000f03c 0x3c4>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
iommu {
|
|
compatible = "nvidia,tegra20-gart";
|
|
reg = <0x7000f024 0x00000018 /* controller registers */
|
|
0x58000000 0x02000000>; /* GART aperture */
|
|
};
|
|
|
|
memory-controller@7000f400 {
|
|
compatible = "nvidia,tegra20-emc";
|
|
reg = <0x7000f400 0x200>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
pcie-controller {
|
|
compatible = "nvidia,tegra20-pcie";
|
|
device_type = "pci";
|
|
reg = <0x80003000 0x00000800 /* PADS registers */
|
|
0x80003800 0x00000200 /* AFI registers */
|
|
0x90000000 0x10000000>; /* configuration space */
|
|
reg-names = "pads", "afi", "cs";
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
|
|
GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
|
interrupt-names = "intr", "msi";
|
|
|
|
bus-range = <0x00 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
|
|
0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
|
|
0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
|
|
0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
|
|
0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
|
|
|
|
clocks = <&tegra_car TEGRA20_CLK_PEX>,
|
|
<&tegra_car TEGRA20_CLK_AFI>,
|
|
<&tegra_car TEGRA20_CLK_PCIE_XCLK>,
|
|
<&tegra_car TEGRA20_CLK_PLL_E>;
|
|
clock-names = "pex", "afi", "pcie_xclk", "pll_e";
|
|
status = "disabled";
|
|
|
|
pci@1,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
|
|
reg = <0x000800 0 0 0 0>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
nvidia,num-lanes = <2>;
|
|
};
|
|
|
|
pci@2,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
|
|
reg = <0x001000 0 0 0 0>;
|
|
status = "disabled";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
nvidia,num-lanes = <2>;
|
|
};
|
|
};
|
|
|
|
usb@c5000000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5000000 0x4000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
nvidia,has-legacy-mode;
|
|
clocks = <&tegra_car TEGRA20_CLK_USBD>;
|
|
nvidia,needs-double-reset;
|
|
nvidia,phy = <&phy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy1: usb-phy@c5000000 {
|
|
compatible = "nvidia,tegra20-usb-phy";
|
|
reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA20_CLK_USBD>,
|
|
<&tegra_car TEGRA20_CLK_PLL_U>,
|
|
<&tegra_car TEGRA20_CLK_CLK_M>,
|
|
<&tegra_car TEGRA20_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "timer", "utmi-pads";
|
|
nvidia,has-legacy-mode;
|
|
nvidia,hssync-start-delay = <9>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <1>;
|
|
nvidia,xcvr-lsrslew = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@c5004000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5004000 0x4000>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "ulpi";
|
|
clocks = <&tegra_car TEGRA20_CLK_USB2>;
|
|
nvidia,phy = <&phy2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy2: usb-phy@c5004000 {
|
|
compatible = "nvidia,tegra20-usb-phy";
|
|
reg = <0xc5004000 0x4000>;
|
|
phy_type = "ulpi";
|
|
clocks = <&tegra_car TEGRA20_CLK_USB2>,
|
|
<&tegra_car TEGRA20_CLK_PLL_U>,
|
|
<&tegra_car TEGRA20_CLK_CDEV2>;
|
|
clock-names = "reg", "pll_u", "ulpi-link";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb@c5008000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5008000 0x4000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA20_CLK_USB3>;
|
|
nvidia,phy = <&phy3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy3: usb-phy@c5008000 {
|
|
compatible = "nvidia,tegra20-usb-phy";
|
|
reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car TEGRA20_CLK_USB3>,
|
|
<&tegra_car TEGRA20_CLK_PLL_U>,
|
|
<&tegra_car TEGRA20_CLK_CLK_M>,
|
|
<&tegra_car TEGRA20_CLK_USBD>;
|
|
clock-names = "reg", "pll_u", "timer", "utmi-pads";
|
|
nvidia,hssync-start-delay = <9>;
|
|
nvidia,idle-wait-delay = <17>;
|
|
nvidia,elastic-limit = <16>;
|
|
nvidia,term-range-adj = <6>;
|
|
nvidia,xcvr-setup = <9>;
|
|
nvidia,xcvr-lsfslew = <2>;
|
|
nvidia,xcvr-lsrslew = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000000 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000000 0x200>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000200 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000200 0x200>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000400 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000400 0x200>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000600 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000600 0x200>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|