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0e526b4d55
Allwinner R40 SoC features a USB OTG port and two USB HOST ports. Add support for the host ports in the DTSI file. The OTG controller still cannot work with existing compatibles, and needs more investigation. So it's not added yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
474 lines
12 KiB
Plaintext
474 lines
12 KiB
Plaintext
/*
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* Copyright 2017 Chen-Yu Tsai <wens@csie.org>
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* Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-r40-ccu.h>
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#include <dt-bindings/reset/sun8i-r40-ccu.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nmi_intc: interrupt-controller@1c00030 {
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compatible = "allwinner,sun7i-a20-sc-nmi";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x01c00030 0x0c>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun8i-r40-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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pinctrl-0 = <&mmc0_pins>;
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pinctrl-names = "default";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,sun8i-r40-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@1c11000 {
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compatible = "allwinner,sun8i-r40-emmc",
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"allwinner,sun50i-a64-emmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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pinctrl-0 = <&mmc2_pins>;
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pinctrl-names = "default";
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc3: mmc@1c12000 {
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compatible = "allwinner,sun8i-r40-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x01c12000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC3>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usbphy: phy@1c13400 {
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compatible = "allwinner,sun8i-r40-usb-phy";
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reg = <0x01c13400 0x14>,
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<0x01c14800 0x4>,
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<0x01c19800 0x4>,
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<0x01c1c800 0x4>;
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reg-names = "phy_ctrl",
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"pmu0",
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"pmu1",
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"pmu2";
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clocks = <&ccu CLK_USB_PHY0>,
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<&ccu CLK_USB_PHY1>,
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<&ccu CLK_USB_PHY2>;
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clock-names = "usb0_phy",
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"usb1_phy",
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"usb2_phy";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY1>,
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<&ccu RST_USB_PHY2>;
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reset-names = "usb0_reset",
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"usb1_reset",
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"usb2_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci1: usb@1c19000 {
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compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
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reg = <0x01c19000 0x100>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI1>;
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resets = <&ccu RST_BUS_EHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@1c19400 {
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compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
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reg = <0x01c19400 0x100>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI1>,
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<&ccu CLK_USB_OHCI1>;
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resets = <&ccu RST_BUS_OHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci2: usb@1c1c000 {
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compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
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reg = <0x01c1c000 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_EHCI2>;
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resets = <&ccu RST_BUS_EHCI2>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci2: usb@1c1c400 {
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compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
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reg = <0x01c1c400 0x100>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI2>,
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<&ccu CLK_USB_OHCI2>;
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resets = <&ccu RST_BUS_OHCI2>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,sun8i-r40-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,sun8i-r40-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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i2c0_pins: i2c0-pins {
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pins = "PB0", "PB1";
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function = "i2c0";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2",
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"PF3", "PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc1_pg_pins: mmc1-pg-pins {
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pins = "PG0", "PG1", "PG2",
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"PG3", "PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC5", "PC6", "PC7", "PC8", "PC9",
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"PC10", "PC11", "PC12", "PC13", "PC14",
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"PC15", "PC24";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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uart0_pb_pins: uart0-pb-pins {
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pins = "PB22", "PB23";
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function = "uart0";
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};
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};
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wdt: watchdog@1c20c90 {
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compatible = "allwinner,sun4i-a10-wdt";
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reg = <0x01c20c90 0x10>;
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};
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uart0: serial@1c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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uart1: serial@1c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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uart2: serial@1c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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uart3: serial@1c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART3>;
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resets = <&ccu RST_BUS_UART3>;
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status = "disabled";
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};
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uart4: serial@1c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART4>;
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resets = <&ccu RST_BUS_UART4>;
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status = "disabled";
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};
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uart5: serial@1c29400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29400 0x400>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART5>;
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resets = <&ccu RST_BUS_UART5>;
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status = "disabled";
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};
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uart6: serial@1c29800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29800 0x400>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART6>;
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resets = <&ccu RST_BUS_UART6>;
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status = "disabled";
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};
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uart7: serial@1c29c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29c00 0x400>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART7>;
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resets = <&ccu RST_BUS_UART7>;
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status = "disabled";
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};
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i2c0: i2c@1c2ac00 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C0>;
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resets = <&ccu RST_BUS_I2C0>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@1c2b000 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C1>;
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resets = <&ccu RST_BUS_I2C1>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c2: i2c@1c2b400 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C2>;
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resets = <&ccu RST_BUS_I2C2>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c3: i2c@1c2b800 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b800 0x400>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C3>;
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resets = <&ccu RST_BUS_I2C3>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c4: i2c@1c2c000 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2c000 0x400>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2C4>;
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resets = <&ccu RST_BUS_I2C4>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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reg = <0x01c81000 0x1000>,
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<0x01c82000 0x1000>,
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<0x01c84000 0x2000>,
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<0x01c86000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|