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This patch adds support in phylib to read/write PLCA configuration for Ethernet PHYs that support the OPEN Alliance "10BASE-T1S PLCA Management Registers" specifications. These can be found at https://www.opensig.org/about/specifications/ Signed-off-by: Piergiorgio Beruto <piergiorgio.beruto@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mdio-open-alliance.h - definition of OPEN Alliance SIG standard registers
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*/
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#ifndef __MDIO_OPEN_ALLIANCE__
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#define __MDIO_OPEN_ALLIANCE__
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#include <linux/mdio.h>
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/* NOTE: all OATC14 registers are located in MDIO_MMD_VEND2 */
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/* Open Alliance TC14 (10BASE-T1S) registers */
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#define MDIO_OATC14_PLCA_IDVER 0xca00 /* PLCA ID and version */
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#define MDIO_OATC14_PLCA_CTRL0 0xca01 /* PLCA Control register 0 */
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#define MDIO_OATC14_PLCA_CTRL1 0xca02 /* PLCA Control register 1 */
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#define MDIO_OATC14_PLCA_STATUS 0xca03 /* PLCA Status register */
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#define MDIO_OATC14_PLCA_TOTMR 0xca04 /* PLCA TO Timer register */
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#define MDIO_OATC14_PLCA_BURST 0xca05 /* PLCA BURST mode register */
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/* Open Alliance TC14 PLCA IDVER register */
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#define MDIO_OATC14_PLCA_IDM 0xff00 /* PLCA MAP ID */
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#define MDIO_OATC14_PLCA_VER 0x00ff /* PLCA MAP version */
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/* Open Alliance TC14 PLCA CTRL0 register */
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#define MDIO_OATC14_PLCA_EN BIT(15) /* PLCA enable */
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#define MDIO_OATC14_PLCA_RST BIT(14) /* PLCA reset */
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/* Open Alliance TC14 PLCA CTRL1 register */
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#define MDIO_OATC14_PLCA_NCNT 0xff00 /* PLCA node count */
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#define MDIO_OATC14_PLCA_ID 0x00ff /* PLCA local node ID */
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/* Open Alliance TC14 PLCA STATUS register */
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#define MDIO_OATC14_PLCA_PST BIT(15) /* PLCA status indication */
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/* Open Alliance TC14 PLCA TOTMR register */
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#define MDIO_OATC14_PLCA_TOT 0x00ff
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/* Open Alliance TC14 PLCA BURST register */
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#define MDIO_OATC14_PLCA_MAXBC 0xff00
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#define MDIO_OATC14_PLCA_BTMR 0x00ff
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/* Version Identifiers */
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#define OATC14_IDM 0x0a00
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#endif /* __MDIO_OPEN_ALLIANCE__ */
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