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ac2527bfc2
Adding a flag for tegra_disable_clean_inv_dcache to flush cache as LoUIS or ALL. After this patch, the v7_flush_dcache_louis is used for CPU hotplug and CPU suspend in CPU power down (e.g. CPU idle power-down mode) case. And the v7_flush_dcache_all is used for CPU cluster power down (e.g. suspend to LP2 mode). Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
177 lines
4.9 KiB
C
177 lines
4.9 KiB
C
/*
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* Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MACH_TEGRA_SLEEP_H
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#define __MACH_TEGRA_SLEEP_H
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#include "iomap.h"
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#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
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+ IO_CPU_VIRT)
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#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
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+ IO_PPSB_VIRT)
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#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
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+ IO_PPSB_VIRT)
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#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
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+ IO_APB_VIRT)
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#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
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/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
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#define PMC_SCRATCH37 0x130
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#define PMC_SCRATCH38 0x134
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#define PMC_SCRATCH39 0x138
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#define PMC_SCRATCH41 0x140
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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#define CPU_RESETTABLE 2
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#define CPU_RESETTABLE_SOON 1
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#define CPU_NOT_RESETTABLE 0
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#endif
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/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
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#define TEGRA_FLUSH_CACHE_LOUIS 0
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#define TEGRA_FLUSH_CACHE_ALL 1
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#ifdef __ASSEMBLY__
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/* returns the offset of the flow controller halt register for a cpu */
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.macro cpu_to_halt_reg rd, rcpu
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cmp \rcpu, #0
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subne \rd, \rcpu, #1
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movne \rd, \rd, lsl #3
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addne \rd, \rd, #0x14
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moveq \rd, #0
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.endm
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/* returns the offset of the flow controller csr register for a cpu */
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.macro cpu_to_csr_reg rd, rcpu
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cmp \rcpu, #0
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subne \rd, \rcpu, #1
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movne \rd, \rd, lsl #3
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addne \rd, \rd, #0x18
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moveq \rd, #8
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.endm
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/* returns the ID of the current processor */
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.macro cpu_id, rd
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mrc p15, 0, \rd, c0, c0, 5
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and \rd, \rd, #0xF
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.endm
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/* loads a 32-bit value into a register without a data access */
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.macro mov32, reg, val
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movw \reg, #:lower16:\val
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movt \reg, #:upper16:\val
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.endm
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/* Marco to check CPU part num */
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.macro check_cpu_part_num part_num, tmp1, tmp2
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mrc p15, 0, \tmp1, c0, c0, 0
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ubfx \tmp1, \tmp1, #4, #12
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mov32 \tmp2, \part_num
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cmp \tmp1, \tmp2
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.endm
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/* Macro to exit SMP coherency. */
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.macro exit_smp, tmp1, tmp2
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mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
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mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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isb
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#ifdef CONFIG_HAVE_ARM_SCU
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check_cpu_part_num 0xc09, \tmp1, \tmp2
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mrceq p15, 0, \tmp1, c0, c0, 5
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andeq \tmp1, \tmp1, #0xF
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moveq \tmp1, \tmp1, lsl #2
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moveq \tmp2, #0xf
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moveq \tmp2, \tmp2, lsl \tmp1
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ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
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streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
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dsb
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#endif
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.endm
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/* Macro to check Tegra revision */
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#define APB_MISC_GP_HIDREV 0x804
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.macro tegra_get_soc_id base, tmp1
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mov32 \tmp1, \base
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ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
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and \tmp1, \tmp1, #0xff00
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mov \tmp1, \tmp1, lsr #8
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.endm
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/* Macro to resume & re-enable L2 cache */
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#ifndef L2X0_CTRL_EN
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#define L2X0_CTRL_EN 1
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#endif
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#ifdef CONFIG_CACHE_L2X0
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.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
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W(adr) \tmp1, \phys_l2x0_saved_regs
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ldr \tmp1, [\tmp1]
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ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
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ldr \tmp3, [\tmp2, #L2X0_CTRL]
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tst \tmp3, #L2X0_CTRL_EN
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bne exit_l2_resume
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ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
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str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL]
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ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
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str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL]
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ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
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str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL]
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ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
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str \tmp3, [\tmp2, #L2X0_POWER_CTRL]
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ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
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str \tmp3, [\tmp2, #L2X0_AUX_CTRL]
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mov \tmp3, #L2X0_CTRL_EN
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str \tmp3, [\tmp2, #L2X0_CTRL]
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exit_l2_resume:
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.endm
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#else /* CONFIG_CACHE_L2X0 */
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.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
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.endm
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#endif /* CONFIG_CACHE_L2X0 */
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#else
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void tegra_pen_lock(void);
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void tegra_pen_unlock(void);
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void tegra_resume(void);
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int tegra_sleep_cpu_finish(unsigned long);
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void tegra_disable_clean_inv_dcache(u32 flag);
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#ifdef CONFIG_HOTPLUG_CPU
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void tegra20_hotplug_shutdown(void);
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void tegra30_hotplug_shutdown(void);
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void tegra_hotplug_init(void);
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#else
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static inline void tegra_hotplug_init(void) {}
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#endif
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void tegra20_cpu_shutdown(int cpu);
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int tegra20_cpu_is_resettable_soon(void);
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void tegra20_cpu_clear_resettable(void);
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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void tegra20_cpu_set_resettable_soon(void);
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#else
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static inline void tegra20_cpu_set_resettable_soon(void) {}
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#endif
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int tegra20_sleep_cpu_secondary_finish(unsigned long);
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void tegra20_tear_down_cpu(void);
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int tegra30_sleep_cpu_secondary_finish(unsigned long);
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void tegra30_tear_down_cpu(void);
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#endif
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#endif
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