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We will set regcache_cache_only true in suspend. As a result, regmap_read will return error when we try to read volatile registers in suspend. Besides, it doesn't make sense to read feedback data when codec is not active. To make userspace happy, this patch returns a cached value shich should be a valid value. Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20201217074556.32370-1-yung-chuan.liao@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
238 lines
8.5 KiB
C
238 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2017 Maxim Integrated */
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#ifndef _MAX98373_H
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#define _MAX98373_H
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#define MAX98373_R2000_SW_RESET 0x2000
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#define MAX98373_R2001_INT_RAW1 0x2001
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#define MAX98373_R2002_INT_RAW2 0x2002
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#define MAX98373_R2003_INT_RAW3 0x2003
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#define MAX98373_R2004_INT_STATE1 0x2004
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#define MAX98373_R2005_INT_STATE2 0x2005
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#define MAX98373_R2006_INT_STATE3 0x2006
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#define MAX98373_R2007_INT_FLAG1 0x2007
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#define MAX98373_R2008_INT_FLAG2 0x2008
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#define MAX98373_R2009_INT_FLAG3 0x2009
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#define MAX98373_R200A_INT_EN1 0x200A
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#define MAX98373_R200B_INT_EN2 0x200B
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#define MAX98373_R200C_INT_EN3 0x200C
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#define MAX98373_R200D_INT_FLAG_CLR1 0x200D
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#define MAX98373_R200E_INT_FLAG_CLR2 0x200E
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#define MAX98373_R200F_INT_FLAG_CLR3 0x200F
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#define MAX98373_R2010_IRQ_CTRL 0x2010
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#define MAX98373_R2014_THERM_WARN_THRESH 0x2014
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#define MAX98373_R2015_THERM_SHDN_THRESH 0x2015
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#define MAX98373_R2016_THERM_HYSTERESIS 0x2016
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#define MAX98373_R2017_THERM_FOLDBACK_SET 0x2017
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#define MAX98373_R2018_THERM_FOLDBACK_EN 0x2018
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#define MAX98373_R201E_PIN_DRIVE_STRENGTH 0x201E
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#define MAX98373_R2020_PCM_TX_HIZ_EN_1 0x2020
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#define MAX98373_R2021_PCM_TX_HIZ_EN_2 0x2021
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#define MAX98373_R2022_PCM_TX_SRC_1 0x2022
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#define MAX98373_R2023_PCM_TX_SRC_2 0x2023
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#define MAX98373_R2024_PCM_DATA_FMT_CFG 0x2024
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#define MAX98373_R2025_AUDIO_IF_MODE 0x2025
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#define MAX98373_R2026_PCM_CLOCK_RATIO 0x2026
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#define MAX98373_R2027_PCM_SR_SETUP_1 0x2027
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#define MAX98373_R2028_PCM_SR_SETUP_2 0x2028
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#define MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 0x2029
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#define MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2 0x202A
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#define MAX98373_R202B_PCM_RX_EN 0x202B
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#define MAX98373_R202C_PCM_TX_EN 0x202C
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#define MAX98373_R202E_ICC_RX_CH_EN_1 0x202E
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#define MAX98373_R202F_ICC_RX_CH_EN_2 0x202F
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#define MAX98373_R2030_ICC_TX_HIZ_EN_1 0x2030
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#define MAX98373_R2031_ICC_TX_HIZ_EN_2 0x2031
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#define MAX98373_R2032_ICC_LINK_EN_CFG 0x2032
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#define MAX98373_R2034_ICC_TX_CNTL 0x2034
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#define MAX98373_R2035_ICC_TX_EN 0x2035
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#define MAX98373_R2036_SOUNDWIRE_CTRL 0x2036
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#define MAX98373_R203D_AMP_DIG_VOL_CTRL 0x203D
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#define MAX98373_R203E_AMP_PATH_GAIN 0x203E
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#define MAX98373_R203F_AMP_DSP_CFG 0x203F
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#define MAX98373_R2040_TONE_GEN_CFG 0x2040
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#define MAX98373_R2041_AMP_CFG 0x2041
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#define MAX98373_R2042_AMP_EDGE_RATE_CFG 0x2042
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#define MAX98373_R2043_AMP_EN 0x2043
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#define MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 0x2046
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#define MAX98373_R2047_IV_SENSE_ADC_EN 0x2047
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#define MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 0x2051
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#define MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG 0x2052
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#define MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG 0x2053
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#define MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK 0x2054
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#define MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK 0x2055
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#define MAX98373_R2056_MEAS_ADC_PVDD_CH_EN 0x2056
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#define MAX98373_R2090_BDE_LVL_HOLD 0x2090
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#define MAX98373_R2091_BDE_GAIN_ATK_REL_RATE 0x2091
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#define MAX98373_R2092_BDE_CLIPPER_MODE 0x2092
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#define MAX98373_R2097_BDE_L1_THRESH 0x2097
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#define MAX98373_R2098_BDE_L2_THRESH 0x2098
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#define MAX98373_R2099_BDE_L3_THRESH 0x2099
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#define MAX98373_R209A_BDE_L4_THRESH 0x209A
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#define MAX98373_R209B_BDE_THRESH_HYST 0x209B
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#define MAX98373_R20A8_BDE_L1_CFG_1 0x20A8
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#define MAX98373_R20A9_BDE_L1_CFG_2 0x20A9
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#define MAX98373_R20AA_BDE_L1_CFG_3 0x20AA
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#define MAX98373_R20AB_BDE_L2_CFG_1 0x20AB
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#define MAX98373_R20AC_BDE_L2_CFG_2 0x20AC
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#define MAX98373_R20AD_BDE_L2_CFG_3 0x20AD
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#define MAX98373_R20AE_BDE_L3_CFG_1 0x20AE
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#define MAX98373_R20AF_BDE_L3_CFG_2 0x20AF
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#define MAX98373_R20B0_BDE_L3_CFG_3 0x20B0
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#define MAX98373_R20B1_BDE_L4_CFG_1 0x20B1
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#define MAX98373_R20B2_BDE_L4_CFG_2 0x20B2
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#define MAX98373_R20B3_BDE_L4_CFG_3 0x20B3
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#define MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE 0x20B4
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#define MAX98373_R20B5_BDE_EN 0x20B5
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#define MAX98373_R20B6_BDE_CUR_STATE_READBACK 0x20B6
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#define MAX98373_R20D1_DHT_CFG 0x20D1
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#define MAX98373_R20D2_DHT_ATTACK_CFG 0x20D2
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#define MAX98373_R20D3_DHT_RELEASE_CFG 0x20D3
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#define MAX98373_R20D4_DHT_EN 0x20D4
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#define MAX98373_R20E0_LIMITER_THRESH_CFG 0x20E0
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#define MAX98373_R20E1_LIMITER_ATK_REL_RATES 0x20E1
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#define MAX98373_R20E2_LIMITER_EN 0x20E2
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#define MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 0x20FE
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#define MAX98373_R20FF_GLOBAL_SHDN 0x20FF
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#define MAX98373_R21FF_REV_ID 0x21FF
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/* MAX98373_R2022_PCM_TX_SRC_1 */
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#define MAX98373_PCM_TX_CH_SRC_A_V_SHIFT (0)
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#define MAX98373_PCM_TX_CH_SRC_A_I_SHIFT (4)
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/* MAX98373_R2024_PCM_DATA_FMT_CFG */
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#define MAX98373_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
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#define MAX98373_PCM_MODE_CFG_FORMAT_SHIFT (3)
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#define MAX98373_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)
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#define MAX98373_PCM_FORMAT_I2S (0x0 << 0)
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#define MAX98373_PCM_FORMAT_LJ (0x1 << 0)
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#define MAX98373_PCM_FORMAT_TDM_MODE0 (0x3 << 0)
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#define MAX98373_PCM_FORMAT_TDM_MODE1 (0x4 << 0)
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#define MAX98373_PCM_FORMAT_TDM_MODE2 (0x5 << 0)
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#define MAX98373_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
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#define MAX98373_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
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#define MAX98373_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
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#define MAX98373_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
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/* MAX98373_R2026_PCM_CLOCK_RATIO */
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#define MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4)
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#define MAX98373_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
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/* MAX98373_R2027_PCM_SR_SETUP_1 */
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#define MAX98373_PCM_SR_SET1_SR_MASK (0xF << 0)
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#define MAX98373_PCM_SR_SET1_SR_8000 (0x0 << 0)
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#define MAX98373_PCM_SR_SET1_SR_11025 (0x1 << 0)
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#define MAX98373_PCM_SR_SET1_SR_12000 (0x2 << 0)
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#define MAX98373_PCM_SR_SET1_SR_16000 (0x3 << 0)
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#define MAX98373_PCM_SR_SET1_SR_22050 (0x4 << 0)
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#define MAX98373_PCM_SR_SET1_SR_24000 (0x5 << 0)
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#define MAX98373_PCM_SR_SET1_SR_32000 (0x6 << 0)
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#define MAX98373_PCM_SR_SET1_SR_44100 (0x7 << 0)
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#define MAX98373_PCM_SR_SET1_SR_48000 (0x8 << 0)
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#define MAX98373_PCM_SR_SET1_SR_88200 (0x9 << 0)
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#define MAX98373_PCM_SR_SET1_SR_96000 (0xA << 0)
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/* MAX98373_R2028_PCM_SR_SETUP_2 */
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#define MAX98373_PCM_SR_SET2_SR_MASK (0xF << 4)
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#define MAX98373_PCM_SR_SET2_SR_SHIFT (4)
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#define MAX98373_PCM_SR_SET2_IVADC_SR_MASK (0xF << 0)
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/* MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 */
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#define MAX98373_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6)
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#define MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6)
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#define MAX98373_PCM_TO_SPK_CH0_SRC_MASK (0xF << 0)
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/* MAX98373_R203E_AMP_PATH_GAIN */
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#define MAX98373_SPK_DIGI_GAIN_MASK (0xF << 4)
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#define MAX98373_SPK_DIGI_GAIN_SHIFT (4)
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#define MAX98373_FS_GAIN_MAX_MASK (0xF << 0)
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#define MAX98373_FS_GAIN_MAX_SHIFT (0)
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/* MAX98373_R203F_AMP_DSP_CFG */
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#define MAX98373_AMP_DSP_CFG_DCBLK_SHIFT (0)
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#define MAX98373_AMP_DSP_CFG_DITH_SHIFT (1)
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#define MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT (2)
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#define MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT (3)
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#define MAX98373_AMP_DSP_CFG_DAC_INV_SHIFT (5)
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#define MAX98373_AMP_VOL_SEL_SHIFT (7)
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/* MAX98373_R2043_AMP_EN */
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#define MAX98373_SPKFB_EN_MASK (0x1 << 1)
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#define MAX98373_SPK_EN_MASK (0x1 << 0)
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#define MAX98373_SPKFB_EN_SHIFT (1)
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/*MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG */
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#define MAX98373_FLT_EN_SHIFT (4)
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/* MAX98373_R20B2_BDE_L4_CFG_2 */
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#define MAX98373_LVL4_MUTE_EN_SHIFT (7)
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#define MAX98373_LVL4_HOLD_EN_SHIFT (6)
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/* MAX98373_R20B5_BDE_EN */
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#define MAX98373_BDE_EN_SHIFT (0)
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/* MAX98373_R20D1_DHT_CFG */
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#define MAX98373_DHT_SPK_GAIN_MIN_SHIFT (4)
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#define MAX98373_DHT_ROT_PNT_SHIFT (0)
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/* MAX98373_R20D2_DHT_ATTACK_CFG */
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#define MAX98373_DHT_ATTACK_STEP_SHIFT (3)
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#define MAX98373_DHT_ATTACK_RATE_SHIFT (0)
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/* MAX98373_R20D3_DHT_RELEASE_CFG */
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#define MAX98373_DHT_RELEASE_STEP_SHIFT (3)
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#define MAX98373_DHT_RELEASE_RATE_SHIFT (0)
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/* MAX98373_R20D4_DHT_EN */
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#define MAX98373_DHT_EN_SHIFT (0)
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/* MAX98373_R20E0_LIMITER_THRESH_CFG */
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#define MAX98373_LIMITER_THRESH_SHIFT (2)
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#define MAX98373_LIMITER_THRESH_SRC_SHIFT (0)
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/* MAX98373_R20E2_LIMITER_EN */
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#define MAX98373_LIMITER_EN_SHIFT (0)
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/* MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG */
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#define MAX98373_CLOCK_MON_SHIFT (0)
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/* MAX98373_R20FF_GLOBAL_SHDN */
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#define MAX98373_GLOBAL_EN_MASK (0x1 << 0)
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/* MAX98373_R2000_SW_RESET */
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#define MAX98373_SOFT_RESET (0x1 << 0)
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struct max98373_cache {
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u32 reg;
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u32 val;
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};
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struct max98373_priv {
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struct regmap *regmap;
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int reset_gpio;
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unsigned int v_slot;
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unsigned int i_slot;
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unsigned int spkfb_slot;
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bool interleave_mode;
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unsigned int ch_size;
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bool tdm_mode;
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/* cache for reading a valid fake feedback value */
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struct max98373_cache *cache;
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int cache_num;
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/* variables to support soundwire */
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struct sdw_slave *slave;
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bool hw_init;
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bool pm_init_once;
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int slot;
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unsigned int rx_mask;
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};
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extern const struct snd_soc_component_driver soc_codec_dev_max98373;
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extern const struct snd_soc_component_driver soc_codec_dev_max98373_sdw;
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void max98373_reset(struct max98373_priv *max98373, struct device *dev);
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void max98373_slot_config(struct device *dev,
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struct max98373_priv *max98373);
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#endif
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