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aaf83d4fc4
The vendor driver code suggests that CR47 patching happens on every channel change for every RF (depending on bit 8 in POD). Due to a bug in their driver (upper bits of RF_Mode get zeroed out, then are examined for 1s when setting some other flags), this isn't actually what happens, and their generic CCK patching routine never takes effect. Some of their RF configurations do include explicit (duplicated) code for CR47 patching though. This patch makes zd1211rw match that behaviour. Signed-off-by: Daniel Drake <dsd@gentoo.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
438 lines
12 KiB
C
438 lines
12 KiB
C
/* zd_rf_al2230.c: Functions for the AL2230 RF controller
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include "zd_rf.h"
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#include "zd_usb.h"
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#include "zd_chip.h"
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static const u32 zd1211_al2230_table[][3] = {
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RF_CHANNEL( 1) = { 0x03f790, 0x033331, 0x00000d, },
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RF_CHANNEL( 2) = { 0x03f790, 0x0b3331, 0x00000d, },
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RF_CHANNEL( 3) = { 0x03e790, 0x033331, 0x00000d, },
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RF_CHANNEL( 4) = { 0x03e790, 0x0b3331, 0x00000d, },
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RF_CHANNEL( 5) = { 0x03f7a0, 0x033331, 0x00000d, },
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RF_CHANNEL( 6) = { 0x03f7a0, 0x0b3331, 0x00000d, },
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RF_CHANNEL( 7) = { 0x03e7a0, 0x033331, 0x00000d, },
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RF_CHANNEL( 8) = { 0x03e7a0, 0x0b3331, 0x00000d, },
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RF_CHANNEL( 9) = { 0x03f7b0, 0x033331, 0x00000d, },
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RF_CHANNEL(10) = { 0x03f7b0, 0x0b3331, 0x00000d, },
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RF_CHANNEL(11) = { 0x03e7b0, 0x033331, 0x00000d, },
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RF_CHANNEL(12) = { 0x03e7b0, 0x0b3331, 0x00000d, },
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RF_CHANNEL(13) = { 0x03f7c0, 0x033331, 0x00000d, },
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RF_CHANNEL(14) = { 0x03e7c0, 0x066661, 0x00000d, },
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};
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static const u32 zd1211b_al2230_table[][3] = {
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RF_CHANNEL( 1) = { 0x09efc0, 0x8cccc0, 0xb00000, },
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RF_CHANNEL( 2) = { 0x09efc0, 0x8cccd0, 0xb00000, },
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RF_CHANNEL( 3) = { 0x09e7c0, 0x8cccc0, 0xb00000, },
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RF_CHANNEL( 4) = { 0x09e7c0, 0x8cccd0, 0xb00000, },
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RF_CHANNEL( 5) = { 0x05efc0, 0x8cccc0, 0xb00000, },
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RF_CHANNEL( 6) = { 0x05efc0, 0x8cccd0, 0xb00000, },
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RF_CHANNEL( 7) = { 0x05e7c0, 0x8cccc0, 0xb00000, },
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RF_CHANNEL( 8) = { 0x05e7c0, 0x8cccd0, 0xb00000, },
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RF_CHANNEL( 9) = { 0x0defc0, 0x8cccc0, 0xb00000, },
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RF_CHANNEL(10) = { 0x0defc0, 0x8cccd0, 0xb00000, },
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RF_CHANNEL(11) = { 0x0de7c0, 0x8cccc0, 0xb00000, },
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RF_CHANNEL(12) = { 0x0de7c0, 0x8cccd0, 0xb00000, },
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RF_CHANNEL(13) = { 0x03efc0, 0x8cccc0, 0xb00000, },
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RF_CHANNEL(14) = { 0x03e7c0, 0x866660, 0xb00000, },
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};
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static const struct zd_ioreq16 zd1211b_ioreqs_shared_1[] = {
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{ CR240, 0x57 }, { CR9, 0xe0 },
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};
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static const struct zd_ioreq16 ioreqs_init_al2230s[] = {
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{ CR47, 0x1e }, /* MARK_002 */
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{ CR106, 0x22 },
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{ CR107, 0x2a }, /* MARK_002 */
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{ CR109, 0x13 }, /* MARK_002 */
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{ CR118, 0xf8 }, /* MARK_002 */
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{ CR119, 0x12 }, { CR122, 0xe0 },
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{ CR128, 0x10 }, /* MARK_001 from 0xe->0x10 */
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{ CR129, 0x0e }, /* MARK_001 from 0xd->0x0e */
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{ CR130, 0x10 }, /* MARK_001 from 0xb->0x0d */
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};
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static int zd1211b_al2230_finalize_rf(struct zd_chip *chip)
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{
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int r;
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR80, 0x30 }, { CR81, 0x30 }, { CR79, 0x58 },
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{ CR12, 0xf0 }, { CR77, 0x1b }, { CR78, 0x58 },
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{ CR203, 0x06 },
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{ },
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{ CR240, 0x80 },
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};
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r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
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if (r)
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return r;
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/* related to antenna selection? */
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if (chip->new_phy_layout) {
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r = zd_iowrite16_locked(chip, 0xe1, CR9);
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if (r)
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return r;
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}
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return zd_iowrite16_locked(chip, 0x06, CR203);
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}
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static int zd1211_al2230_init_hw(struct zd_rf *rf)
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{
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int r;
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struct zd_chip *chip = zd_rf_to_chip(rf);
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static const struct zd_ioreq16 ioreqs_init[] = {
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{ CR15, 0x20 }, { CR23, 0x40 }, { CR24, 0x20 },
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{ CR26, 0x11 }, { CR28, 0x3e }, { CR29, 0x00 },
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{ CR44, 0x33 }, { CR106, 0x2a }, { CR107, 0x1a },
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{ CR109, 0x09 }, { CR110, 0x27 }, { CR111, 0x2b },
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{ CR112, 0x2b }, { CR119, 0x0a }, { CR10, 0x89 },
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/* for newest (3rd cut) AL2300 */
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{ CR17, 0x28 },
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{ CR26, 0x93 }, { CR34, 0x30 },
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/* for newest (3rd cut) AL2300 */
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{ CR35, 0x3e },
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{ CR41, 0x24 }, { CR44, 0x32 },
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/* for newest (3rd cut) AL2300 */
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{ CR46, 0x96 },
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{ CR47, 0x1e }, { CR79, 0x58 }, { CR80, 0x30 },
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{ CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
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{ CR92, 0x0a }, { CR99, 0x28 }, { CR100, 0x00 },
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{ CR101, 0x13 }, { CR102, 0x27 }, { CR106, 0x24 },
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{ CR107, 0x2a }, { CR109, 0x09 }, { CR110, 0x13 },
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{ CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
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{ CR114, 0x27 },
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/* for newest (3rd cut) AL2300 */
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{ CR115, 0x24 },
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{ CR116, 0x24 }, { CR117, 0xf4 }, { CR118, 0xfc },
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{ CR119, 0x10 }, { CR120, 0x4f }, { CR121, 0x77 },
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{ CR122, 0xe0 }, { CR137, 0x88 }, { CR252, 0xff },
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{ CR253, 0xff },
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};
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static const struct zd_ioreq16 ioreqs_pll[] = {
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/* shdnb(PLL_ON)=0 */
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{ CR251, 0x2f },
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/* shdnb(PLL_ON)=1 */
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{ CR251, 0x3f },
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{ CR138, 0x28 }, { CR203, 0x06 },
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};
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static const u32 rv1[] = {
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/* Channel 1 */
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0x03f790,
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0x033331,
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0x00000d,
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0x0b3331,
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0x03b812,
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0x00fff3,
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};
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static const u32 rv2[] = {
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0x000da4,
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0x0f4dc5, /* fix freq shift, 0x04edc5 */
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0x0805b6,
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0x011687,
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0x000688,
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0x0403b9, /* external control TX power (CR31) */
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0x00dbba,
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0x00099b,
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0x0bdffc,
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0x00000d,
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0x00500f,
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};
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static const u32 rv3[] = {
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0x00d00f,
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0x004c0f,
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0x00540f,
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0x00700f,
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0x00500f,
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};
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r = zd_iowrite16a_locked(chip, ioreqs_init, ARRAY_SIZE(ioreqs_init));
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if (r)
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return r;
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if (chip->al2230s_bit) {
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r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
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ARRAY_SIZE(ioreqs_init_al2230s));
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if (r)
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return r;
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}
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r = zd_rfwritev_locked(chip, rv1, ARRAY_SIZE(rv1), RF_RV_BITS);
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if (r)
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return r;
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/* improve band edge for AL2230S */
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if (chip->al2230s_bit)
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r = zd_rfwrite_locked(chip, 0x000824, RF_RV_BITS);
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else
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r = zd_rfwrite_locked(chip, 0x0005a4, RF_RV_BITS);
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if (r)
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return r;
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r = zd_rfwritev_locked(chip, rv2, ARRAY_SIZE(rv2), RF_RV_BITS);
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if (r)
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return r;
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r = zd_iowrite16a_locked(chip, ioreqs_pll, ARRAY_SIZE(ioreqs_pll));
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if (r)
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return r;
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r = zd_rfwritev_locked(chip, rv3, ARRAY_SIZE(rv3), RF_RV_BITS);
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if (r)
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return r;
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return 0;
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}
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static int zd1211b_al2230_init_hw(struct zd_rf *rf)
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{
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int r;
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struct zd_chip *chip = zd_rf_to_chip(rf);
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static const struct zd_ioreq16 ioreqs1[] = {
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{ CR10, 0x89 }, { CR15, 0x20 },
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{ CR17, 0x2B }, /* for newest(3rd cut) AL2230 */
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{ CR23, 0x40 }, { CR24, 0x20 }, { CR26, 0x93 },
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{ CR28, 0x3e }, { CR29, 0x00 },
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{ CR33, 0x28 }, /* 5621 */
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{ CR34, 0x30 },
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{ CR35, 0x3e }, /* for newest(3rd cut) AL2230 */
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{ CR41, 0x24 }, { CR44, 0x32 },
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{ CR46, 0x99 }, /* for newest(3rd cut) AL2230 */
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{ CR47, 0x1e },
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/* ZD1211B 05.06.10 */
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{ CR48, 0x06 }, { CR49, 0xf9 }, { CR51, 0x01 },
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{ CR52, 0x80 }, { CR53, 0x7e }, { CR65, 0x00 },
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{ CR66, 0x00 }, { CR67, 0x00 }, { CR68, 0x00 },
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{ CR69, 0x28 },
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{ CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
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{ CR87, 0x0a }, { CR89, 0x04 },
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{ CR91, 0x00 }, /* 5621 */
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{ CR92, 0x0a },
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{ CR98, 0x8d }, /* 4804, for 1212 new algorithm */
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{ CR99, 0x00 }, /* 5621 */
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{ CR101, 0x13 }, { CR102, 0x27 },
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{ CR106, 0x24 }, /* for newest(3rd cut) AL2230 */
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{ CR107, 0x2a },
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{ CR109, 0x13 }, /* 4804, for 1212 new algorithm */
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{ CR110, 0x1f }, /* 4804, for 1212 new algorithm */
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{ CR111, 0x1f }, { CR112, 0x1f }, { CR113, 0x27 },
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{ CR114, 0x27 },
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{ CR115, 0x26 }, /* 24->26 at 4902 for newest(3rd cut) AL2230 */
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{ CR116, 0x24 },
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{ CR117, 0xfa }, /* for 1211b */
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{ CR118, 0xfa }, /* for 1211b */
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{ CR119, 0x10 },
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{ CR120, 0x4f },
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{ CR121, 0x6c }, /* for 1211b */
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{ CR122, 0xfc }, /* E0->FC at 4902 */
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{ CR123, 0x57 }, /* 5623 */
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{ CR125, 0xad }, /* 4804, for 1212 new algorithm */
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{ CR126, 0x6c }, /* 5614 */
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{ CR127, 0x03 }, /* 4804, for 1212 new algorithm */
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{ CR137, 0x50 }, /* 5614 */
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{ CR138, 0xa8 },
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{ CR144, 0xac }, /* 5621 */
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{ CR150, 0x0d }, { CR252, 0x34 }, { CR253, 0x34 },
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};
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static const u32 rv1[] = {
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0x8cccd0,
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0x481dc0,
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0xcfff00,
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0x25a000,
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};
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static const u32 rv2[] = {
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/* To improve AL2230 yield, improve phase noise, 4713 */
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0x25a000,
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0xa3b2f0,
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0x6da010, /* Reg6 update for MP versio */
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0xe36280, /* Modified by jxiao for Bor-Chin on 2004/08/02 */
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0x116000,
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0x9dc020, /* External control TX power (CR31) */
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0x5ddb00, /* RegA update for MP version */
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0xd99000, /* RegB update for MP version */
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0x3ffbd0, /* RegC update for MP version */
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0xb00000, /* RegD update for MP version */
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/* improve phase noise and remove phase calibration,4713 */
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0xf01a00,
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};
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static const struct zd_ioreq16 ioreqs2[] = {
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{ CR251, 0x2f }, /* shdnb(PLL_ON)=0 */
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{ CR251, 0x7f }, /* shdnb(PLL_ON)=1 */
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};
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static const u32 rv3[] = {
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/* To improve AL2230 yield, 4713 */
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0xf01b00,
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0xf01e00,
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0xf01a00,
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};
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static const struct zd_ioreq16 ioreqs3[] = {
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/* related to 6M band edge patching, happens unconditionally */
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{ CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
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};
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r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
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ARRAY_SIZE(zd1211b_ioreqs_shared_1));
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if (r)
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return r;
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r = zd_iowrite16a_locked(chip, ioreqs1, ARRAY_SIZE(ioreqs1));
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if (r)
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return r;
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if (chip->al2230s_bit) {
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r = zd_iowrite16a_locked(chip, ioreqs_init_al2230s,
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ARRAY_SIZE(ioreqs_init_al2230s));
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if (r)
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return r;
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}
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r = zd_rfwritev_cr_locked(chip, zd1211b_al2230_table[0], 3);
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if (r)
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return r;
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r = zd_rfwritev_cr_locked(chip, rv1, ARRAY_SIZE(rv1));
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if (r)
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return r;
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if (chip->al2230s_bit)
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r = zd_rfwrite_locked(chip, 0x241000, RF_RV_BITS);
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else
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r = zd_rfwrite_locked(chip, 0x25a000, RF_RV_BITS);
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if (r)
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return r;
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r = zd_rfwritev_cr_locked(chip, rv2, ARRAY_SIZE(rv2));
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if (r)
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return r;
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r = zd_iowrite16a_locked(chip, ioreqs2, ARRAY_SIZE(ioreqs2));
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if (r)
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return r;
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r = zd_rfwritev_cr_locked(chip, rv3, ARRAY_SIZE(rv3));
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if (r)
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return r;
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r = zd_iowrite16a_locked(chip, ioreqs3, ARRAY_SIZE(ioreqs3));
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if (r)
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return r;
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return zd1211b_al2230_finalize_rf(chip);
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}
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static int zd1211_al2230_set_channel(struct zd_rf *rf, u8 channel)
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{
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int r;
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const u32 *rv = zd1211_al2230_table[channel-1];
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struct zd_chip *chip = zd_rf_to_chip(rf);
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR138, 0x28 },
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{ CR203, 0x06 },
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};
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r = zd_rfwritev_locked(chip, rv, 3, RF_RV_BITS);
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if (r)
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return r;
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return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
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}
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static int zd1211b_al2230_set_channel(struct zd_rf *rf, u8 channel)
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{
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int r;
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const u32 *rv = zd1211b_al2230_table[channel-1];
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struct zd_chip *chip = zd_rf_to_chip(rf);
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r = zd_iowrite16a_locked(chip, zd1211b_ioreqs_shared_1,
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ARRAY_SIZE(zd1211b_ioreqs_shared_1));
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if (r)
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return r;
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r = zd_rfwritev_cr_locked(chip, rv, 3);
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if (r)
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return r;
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return zd1211b_al2230_finalize_rf(chip);
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}
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static int zd1211_al2230_switch_radio_on(struct zd_rf *rf)
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{
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struct zd_chip *chip = zd_rf_to_chip(rf);
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR11, 0x00 },
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{ CR251, 0x3f },
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};
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return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
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}
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static int zd1211b_al2230_switch_radio_on(struct zd_rf *rf)
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{
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struct zd_chip *chip = zd_rf_to_chip(rf);
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR11, 0x00 },
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{ CR251, 0x7f },
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};
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return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
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}
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static int al2230_switch_radio_off(struct zd_rf *rf)
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{
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struct zd_chip *chip = zd_rf_to_chip(rf);
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static const struct zd_ioreq16 ioreqs[] = {
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{ CR11, 0x04 },
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{ CR251, 0x2f },
|
|
};
|
|
|
|
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
|
|
}
|
|
|
|
int zd_rf_init_al2230(struct zd_rf *rf)
|
|
{
|
|
struct zd_chip *chip = zd_rf_to_chip(rf);
|
|
|
|
rf->switch_radio_off = al2230_switch_radio_off;
|
|
if (chip->is_zd1211b) {
|
|
rf->init_hw = zd1211b_al2230_init_hw;
|
|
rf->set_channel = zd1211b_al2230_set_channel;
|
|
rf->switch_radio_on = zd1211b_al2230_switch_radio_on;
|
|
} else {
|
|
rf->init_hw = zd1211_al2230_init_hw;
|
|
rf->set_channel = zd1211_al2230_set_channel;
|
|
rf->switch_radio_on = zd1211_al2230_switch_radio_on;
|
|
}
|
|
rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
|
|
rf->patch_cck_gain = 1;
|
|
return 0;
|
|
}
|