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81279f5d08
Add driver for the StarFive JH7110 Image-Signal-Process clock controller. And these clock controllers should power on and enable the clocks from SYSCRG before registering. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
18 lines
406 B
C
18 lines
406 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __CLK_STARFIVE_JH7110_H
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#define __CLK_STARFIVE_JH7110_H
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#include "clk-starfive-jh71x0.h"
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/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
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struct jh7110_top_sysclk {
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struct clk_bulk_data *top_clks;
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int top_clks_num;
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};
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int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
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const char *adev_name,
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u32 adev_id);
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#endif
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