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bad9a43a20
The genirq layer expects a 0 in case that the retrigger function is not able to resend the irq in hardware, but the code is returning -ENXIO. Fix it. [ tglx: Reworked comment and changelog ] Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1363734349-32635-1-git-send-email-sboyd@codeaurora.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
847 lines
21 KiB
C
847 lines
21 KiB
C
/*
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* linux/arch/arm/common/gic.c
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*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Interrupt architecture for the GIC:
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*
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* o There is one Interrupt Distributor, which receives interrupts
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* from system devices and sends them to the Interrupt Controllers.
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*
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* o There is one CPU Interface per CPU, which sends interrupts sent
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* by the Distributor, and interrupts generated locally, to the
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* associated CPU. The base address of the CPU interface is usually
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* aliased so that the same address points to different chips depending
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* on the CPU it is accessed from.
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*
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* Note that IRQs 0-31 are special - they are local to each CPU.
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* As such, the enable set/clear, pending set/clear and active bit
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* registers are banked per-cpu for these sources.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include <linux/cpu_pm.h>
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#include <linux/cpumask.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/irq.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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union gic_base {
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void __iomem *common_base;
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void __percpu __iomem **percpu_base;
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};
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struct gic_chip_data {
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union gic_base dist_base;
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union gic_base cpu_base;
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#ifdef CONFIG_CPU_PM
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u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
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u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
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u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
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u32 __percpu *saved_ppi_enable;
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u32 __percpu *saved_ppi_conf;
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#endif
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struct irq_domain *domain;
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unsigned int gic_irqs;
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#ifdef CONFIG_GIC_NON_BANKED
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void __iomem *(*get_base)(union gic_base *);
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#endif
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};
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static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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/*
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* The GIC mapping of CPU interfaces does not necessarily match
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* the logical CPU numbering. Let's use a mapping as returned
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* by the GIC itself.
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*/
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#define NR_GIC_CPU_IF 8
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static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
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/*
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* Supported arch specific GIC irq extension.
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* Default make them NULL.
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*/
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struct irq_chip gic_arch_extn = {
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.irq_eoi = NULL,
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.irq_mask = NULL,
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.irq_unmask = NULL,
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.irq_retrigger = NULL,
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.irq_set_type = NULL,
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.irq_set_wake = NULL,
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};
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#ifndef MAX_GIC_NR
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#define MAX_GIC_NR 1
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#endif
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static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
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#ifdef CONFIG_GIC_NON_BANKED
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static void __iomem *gic_get_percpu_base(union gic_base *base)
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{
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return *__this_cpu_ptr(base->percpu_base);
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}
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static void __iomem *gic_get_common_base(union gic_base *base)
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{
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return base->common_base;
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}
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static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
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{
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return data->get_base(&data->dist_base);
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}
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static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
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{
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return data->get_base(&data->cpu_base);
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}
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static inline void gic_set_base_accessor(struct gic_chip_data *data,
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void __iomem *(*f)(union gic_base *))
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{
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data->get_base = f;
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}
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#else
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#define gic_data_dist_base(d) ((d)->dist_base.common_base)
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#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
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#define gic_set_base_accessor(d,f)
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#endif
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static inline void __iomem *gic_dist_base(struct irq_data *d)
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{
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struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
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return gic_data_dist_base(gic_data);
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}
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static inline void __iomem *gic_cpu_base(struct irq_data *d)
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{
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struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
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return gic_data_cpu_base(gic_data);
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}
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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return d->hwirq;
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}
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/*
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* Routines to acknowledge, disable and enable interrupts
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*/
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static void gic_mask_irq(struct irq_data *d)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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raw_spin_lock(&irq_controller_lock);
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writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
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if (gic_arch_extn.irq_mask)
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gic_arch_extn.irq_mask(d);
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raw_spin_unlock(&irq_controller_lock);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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raw_spin_lock(&irq_controller_lock);
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if (gic_arch_extn.irq_unmask)
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gic_arch_extn.irq_unmask(d);
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writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
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raw_spin_unlock(&irq_controller_lock);
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}
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static void gic_eoi_irq(struct irq_data *d)
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{
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if (gic_arch_extn.irq_eoi) {
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raw_spin_lock(&irq_controller_lock);
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gic_arch_extn.irq_eoi(d);
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raw_spin_unlock(&irq_controller_lock);
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}
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writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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void __iomem *base = gic_dist_base(d);
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unsigned int gicirq = gic_irq(d);
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u32 enablemask = 1 << (gicirq % 32);
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u32 enableoff = (gicirq / 32) * 4;
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u32 confmask = 0x2 << ((gicirq % 16) * 2);
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u32 confoff = (gicirq / 16) * 4;
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bool enabled = false;
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u32 val;
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/* Interrupt configuration for SGIs can't be changed */
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if (gicirq < 16)
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return -EINVAL;
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if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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raw_spin_lock(&irq_controller_lock);
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if (gic_arch_extn.irq_set_type)
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gic_arch_extn.irq_set_type(d, type);
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val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
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if (type == IRQ_TYPE_LEVEL_HIGH)
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val &= ~confmask;
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else if (type == IRQ_TYPE_EDGE_RISING)
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val |= confmask;
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/*
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* As recommended by the spec, disable the interrupt before changing
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* the configuration
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*/
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if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
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enabled = true;
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}
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writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
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if (enabled)
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
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raw_spin_unlock(&irq_controller_lock);
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return 0;
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}
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static int gic_retrigger(struct irq_data *d)
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{
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if (gic_arch_extn.irq_retrigger)
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return gic_arch_extn.irq_retrigger(d);
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/* the genirq layer expects 0 if we can't retrigger in hardware */
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return 0;
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}
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#ifdef CONFIG_SMP
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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bool force)
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{
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
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unsigned int shift = (gic_irq(d) % 4) * 8;
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unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
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u32 val, mask, bit;
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if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
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return -EINVAL;
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mask = 0xff << shift;
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bit = gic_cpu_map[cpu] << shift;
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raw_spin_lock(&irq_controller_lock);
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val = readl_relaxed(reg) & ~mask;
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writel_relaxed(val | bit, reg);
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raw_spin_unlock(&irq_controller_lock);
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return IRQ_SET_MASK_OK;
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}
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#endif
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#ifdef CONFIG_PM
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static int gic_set_wake(struct irq_data *d, unsigned int on)
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{
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int ret = -ENXIO;
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if (gic_arch_extn.irq_set_wake)
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ret = gic_arch_extn.irq_set_wake(d, on);
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return ret;
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}
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#else
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#define gic_set_wake NULL
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#endif
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static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
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{
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u32 irqstat, irqnr;
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struct gic_chip_data *gic = &gic_data[0];
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void __iomem *cpu_base = gic_data_cpu_base(gic);
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do {
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irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
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irqnr = irqstat & ~0x1c00;
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if (likely(irqnr > 15 && irqnr < 1021)) {
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irqnr = irq_find_mapping(gic->domain, irqnr);
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handle_IRQ(irqnr, regs);
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continue;
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}
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if (irqnr < 16) {
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writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
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#ifdef CONFIG_SMP
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handle_IPI(irqnr, regs);
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#endif
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continue;
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}
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break;
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} while (1);
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}
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static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct gic_chip_data *chip_data = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned int cascade_irq, gic_irq;
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unsigned long status;
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chained_irq_enter(chip, desc);
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raw_spin_lock(&irq_controller_lock);
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status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
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raw_spin_unlock(&irq_controller_lock);
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gic_irq = (status & 0x3ff);
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if (gic_irq == 1023)
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goto out;
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cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
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if (unlikely(gic_irq < 32 || gic_irq > 1020))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip gic_chip = {
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.name = "GIC",
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.irq_mask = gic_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoi_irq,
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.irq_set_type = gic_set_type,
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.irq_retrigger = gic_retrigger,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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.irq_set_wake = gic_set_wake,
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};
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void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
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{
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
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BUG();
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irq_set_chained_handler(irq, gic_handle_cascade_irq);
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}
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static u8 gic_get_cpumask(struct gic_chip_data *gic)
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{
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void __iomem *base = gic_data_dist_base(gic);
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u32 mask, i;
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for (i = mask = 0; i < 32; i += 4) {
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mask = readl_relaxed(base + GIC_DIST_TARGET + i);
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mask |= mask >> 16;
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mask |= mask >> 8;
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if (mask)
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break;
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}
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if (!mask)
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pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
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return mask;
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}
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static void __init gic_dist_init(struct gic_chip_data *gic)
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{
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unsigned int i;
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u32 cpumask;
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unsigned int gic_irqs = gic->gic_irqs;
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void __iomem *base = gic_data_dist_base(gic);
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writel_relaxed(0, base + GIC_DIST_CTRL);
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < gic_irqs; i += 16)
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writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
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/*
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* Set all global interrupts to this CPU only.
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*/
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cpumask = gic_get_cpumask(gic);
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
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/*
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* Set priority on all global interrupts.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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/*
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* Disable all interrupts. Leave the PPI and SGIs alone
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* as these enables are banked registers.
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*/
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for (i = 32; i < gic_irqs; i += 32)
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writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
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writel_relaxed(1, base + GIC_DIST_CTRL);
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}
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static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
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{
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void __iomem *dist_base = gic_data_dist_base(gic);
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void __iomem *base = gic_data_cpu_base(gic);
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unsigned int cpu_mask, cpu = smp_processor_id();
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int i;
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/*
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* Get what the GIC says our CPU mask is.
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*/
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BUG_ON(cpu >= NR_GIC_CPU_IF);
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cpu_mask = gic_get_cpumask(gic);
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gic_cpu_map[cpu] = cpu_mask;
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/*
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* Clear our mask from the other map entries in case they're
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* still undefined.
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*/
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for (i = 0; i < NR_GIC_CPU_IF; i++)
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if (i != cpu)
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gic_cpu_map[i] &= ~cpu_mask;
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/*
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* Deal with the banked PPI and SGI interrupts - disable all
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* PPI interrupts, ensure all SGI interrupts are enabled.
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*/
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writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
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writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < 32; i += 4)
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writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
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writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
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writel_relaxed(1, base + GIC_CPU_CTRL);
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}
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#ifdef CONFIG_CPU_PM
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/*
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* Saves the GIC distributor registers during suspend or idle. Must be called
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* with interrupts disabled but before powering down the GIC. After calling
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* this function, no interrupts will be delivered by the GIC, and another
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* platform-specific wakeup source must be enabled.
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*/
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static void gic_dist_save(unsigned int gic_nr)
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{
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unsigned int gic_irqs;
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void __iomem *dist_base;
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int i;
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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gic_irqs = gic_data[gic_nr].gic_irqs;
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dist_base = gic_data_dist_base(&gic_data[gic_nr]);
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if (!dist_base)
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return;
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
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gic_data[gic_nr].saved_spi_conf[i] =
|
|
readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
|
|
gic_data[gic_nr].saved_spi_target[i] =
|
|
readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
|
|
gic_data[gic_nr].saved_spi_enable[i] =
|
|
readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
|
}
|
|
|
|
/*
|
|
* Restores the GIC distributor registers during resume or when coming out of
|
|
* idle. Must be called before enabling interrupts. If a level interrupt
|
|
* that occured while the GIC was suspended is still present, it will be
|
|
* handled normally, but any edge interrupts that occured will not be seen by
|
|
* the GIC and need to be handled by the platform-specific wakeup source.
|
|
*/
|
|
static void gic_dist_restore(unsigned int gic_nr)
|
|
{
|
|
unsigned int gic_irqs;
|
|
unsigned int i;
|
|
void __iomem *dist_base;
|
|
|
|
if (gic_nr >= MAX_GIC_NR)
|
|
BUG();
|
|
|
|
gic_irqs = gic_data[gic_nr].gic_irqs;
|
|
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
|
|
|
if (!dist_base)
|
|
return;
|
|
|
|
writel_relaxed(0, dist_base + GIC_DIST_CTRL);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
|
|
writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
|
|
dist_base + GIC_DIST_CONFIG + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
|
|
writel_relaxed(0xa0a0a0a0,
|
|
dist_base + GIC_DIST_PRI + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
|
|
writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
|
|
dist_base + GIC_DIST_TARGET + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
|
|
writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
|
|
dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
|
|
|
writel_relaxed(1, dist_base + GIC_DIST_CTRL);
|
|
}
|
|
|
|
static void gic_cpu_save(unsigned int gic_nr)
|
|
{
|
|
int i;
|
|
u32 *ptr;
|
|
void __iomem *dist_base;
|
|
void __iomem *cpu_base;
|
|
|
|
if (gic_nr >= MAX_GIC_NR)
|
|
BUG();
|
|
|
|
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
|
cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
|
|
|
|
if (!dist_base || !cpu_base)
|
|
return;
|
|
|
|
ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
|
|
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
|
|
ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
|
|
|
ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
|
|
for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
|
|
ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
|
|
|
|
}
|
|
|
|
static void gic_cpu_restore(unsigned int gic_nr)
|
|
{
|
|
int i;
|
|
u32 *ptr;
|
|
void __iomem *dist_base;
|
|
void __iomem *cpu_base;
|
|
|
|
if (gic_nr >= MAX_GIC_NR)
|
|
BUG();
|
|
|
|
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
|
cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
|
|
|
|
if (!dist_base || !cpu_base)
|
|
return;
|
|
|
|
ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
|
|
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
|
|
writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
|
|
|
ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
|
|
for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
|
|
writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
|
|
writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
|
|
|
|
writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
|
|
writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
|
|
}
|
|
|
|
static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MAX_GIC_NR; i++) {
|
|
#ifdef CONFIG_GIC_NON_BANKED
|
|
/* Skip over unused GICs */
|
|
if (!gic_data[i].get_base)
|
|
continue;
|
|
#endif
|
|
switch (cmd) {
|
|
case CPU_PM_ENTER:
|
|
gic_cpu_save(i);
|
|
break;
|
|
case CPU_PM_ENTER_FAILED:
|
|
case CPU_PM_EXIT:
|
|
gic_cpu_restore(i);
|
|
break;
|
|
case CPU_CLUSTER_PM_ENTER:
|
|
gic_dist_save(i);
|
|
break;
|
|
case CPU_CLUSTER_PM_ENTER_FAILED:
|
|
case CPU_CLUSTER_PM_EXIT:
|
|
gic_dist_restore(i);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block gic_notifier_block = {
|
|
.notifier_call = gic_notifier,
|
|
};
|
|
|
|
static void __init gic_pm_init(struct gic_chip_data *gic)
|
|
{
|
|
gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
|
|
sizeof(u32));
|
|
BUG_ON(!gic->saved_ppi_enable);
|
|
|
|
gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
|
|
sizeof(u32));
|
|
BUG_ON(!gic->saved_ppi_conf);
|
|
|
|
if (gic == &gic_data[0])
|
|
cpu_pm_register_notifier(&gic_notifier_block);
|
|
}
|
|
#else
|
|
static void __init gic_pm_init(struct gic_chip_data *gic)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMP
|
|
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
|
|
{
|
|
int cpu;
|
|
unsigned long map = 0;
|
|
|
|
/* Convert our logical CPU mask into a physical one. */
|
|
for_each_cpu(cpu, mask)
|
|
map |= gic_cpu_map[cpu];
|
|
|
|
/*
|
|
* Ensure that stores to Normal memory are visible to the
|
|
* other CPUs before issuing the IPI.
|
|
*/
|
|
dsb();
|
|
|
|
/* this always happens on GIC0 */
|
|
writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
|
|
}
|
|
#endif
|
|
|
|
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
if (hw < 32) {
|
|
irq_set_percpu_devid(irq);
|
|
irq_set_chip_and_handler(irq, &gic_chip,
|
|
handle_percpu_devid_irq);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
|
|
} else {
|
|
irq_set_chip_and_handler(irq, &gic_chip,
|
|
handle_fasteoi_irq);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
|
}
|
|
irq_set_chip_data(irq, d->host_data);
|
|
return 0;
|
|
}
|
|
|
|
static int gic_irq_domain_xlate(struct irq_domain *d,
|
|
struct device_node *controller,
|
|
const u32 *intspec, unsigned int intsize,
|
|
unsigned long *out_hwirq, unsigned int *out_type)
|
|
{
|
|
if (d->of_node != controller)
|
|
return -EINVAL;
|
|
if (intsize < 3)
|
|
return -EINVAL;
|
|
|
|
/* Get the interrupt number and add 16 to skip over SGIs */
|
|
*out_hwirq = intspec[1] + 16;
|
|
|
|
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
|
|
if (!intspec[0])
|
|
*out_hwirq += 16;
|
|
|
|
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
|
|
return 0;
|
|
}
|
|
|
|
const struct irq_domain_ops gic_irq_domain_ops = {
|
|
.map = gic_irq_domain_map,
|
|
.xlate = gic_irq_domain_xlate,
|
|
};
|
|
|
|
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|
void __iomem *dist_base, void __iomem *cpu_base,
|
|
u32 percpu_offset, struct device_node *node)
|
|
{
|
|
irq_hw_number_t hwirq_base;
|
|
struct gic_chip_data *gic;
|
|
int gic_irqs, irq_base, i;
|
|
|
|
BUG_ON(gic_nr >= MAX_GIC_NR);
|
|
|
|
gic = &gic_data[gic_nr];
|
|
#ifdef CONFIG_GIC_NON_BANKED
|
|
if (percpu_offset) { /* Frankein-GIC without banked registers... */
|
|
unsigned int cpu;
|
|
|
|
gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
|
|
gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
|
|
if (WARN_ON(!gic->dist_base.percpu_base ||
|
|
!gic->cpu_base.percpu_base)) {
|
|
free_percpu(gic->dist_base.percpu_base);
|
|
free_percpu(gic->cpu_base.percpu_base);
|
|
return;
|
|
}
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
unsigned long offset = percpu_offset * cpu_logical_map(cpu);
|
|
*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
|
|
*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
|
|
}
|
|
|
|
gic_set_base_accessor(gic, gic_get_percpu_base);
|
|
} else
|
|
#endif
|
|
{ /* Normal, sane GIC... */
|
|
WARN(percpu_offset,
|
|
"GIC_NON_BANKED not enabled, ignoring %08x offset!",
|
|
percpu_offset);
|
|
gic->dist_base.common_base = dist_base;
|
|
gic->cpu_base.common_base = cpu_base;
|
|
gic_set_base_accessor(gic, gic_get_common_base);
|
|
}
|
|
|
|
/*
|
|
* Initialize the CPU interface map to all CPUs.
|
|
* It will be refined as each CPU probes its ID.
|
|
*/
|
|
for (i = 0; i < NR_GIC_CPU_IF; i++)
|
|
gic_cpu_map[i] = 0xff;
|
|
|
|
/*
|
|
* For primary GICs, skip over SGIs.
|
|
* For secondary GICs, skip over PPIs, too.
|
|
*/
|
|
if (gic_nr == 0 && (irq_start & 31) > 0) {
|
|
hwirq_base = 16;
|
|
if (irq_start != -1)
|
|
irq_start = (irq_start & ~31) + 16;
|
|
} else {
|
|
hwirq_base = 32;
|
|
}
|
|
|
|
/*
|
|
* Find out how many interrupts are supported.
|
|
* The GIC only supports up to 1020 interrupt sources.
|
|
*/
|
|
gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
|
|
gic_irqs = (gic_irqs + 1) * 32;
|
|
if (gic_irqs > 1020)
|
|
gic_irqs = 1020;
|
|
gic->gic_irqs = gic_irqs;
|
|
|
|
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
|
|
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
|
|
if (IS_ERR_VALUE(irq_base)) {
|
|
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
|
|
irq_start);
|
|
irq_base = irq_start;
|
|
}
|
|
gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
|
|
hwirq_base, &gic_irq_domain_ops, gic);
|
|
if (WARN_ON(!gic->domain))
|
|
return;
|
|
|
|
#ifdef CONFIG_SMP
|
|
set_smp_cross_call(gic_raise_softirq);
|
|
#endif
|
|
|
|
set_handle_irq(gic_handle_irq);
|
|
|
|
gic_chip.flags |= gic_arch_extn.flags;
|
|
gic_dist_init(gic);
|
|
gic_cpu_init(gic);
|
|
gic_pm_init(gic);
|
|
}
|
|
|
|
void __cpuinit gic_secondary_init(unsigned int gic_nr)
|
|
{
|
|
BUG_ON(gic_nr >= MAX_GIC_NR);
|
|
|
|
gic_cpu_init(&gic_data[gic_nr]);
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static int gic_cnt __initdata = 0;
|
|
|
|
int __init gic_of_init(struct device_node *node, struct device_node *parent)
|
|
{
|
|
void __iomem *cpu_base;
|
|
void __iomem *dist_base;
|
|
u32 percpu_offset;
|
|
int irq;
|
|
|
|
if (WARN_ON(!node))
|
|
return -ENODEV;
|
|
|
|
dist_base = of_iomap(node, 0);
|
|
WARN(!dist_base, "unable to map gic dist registers\n");
|
|
|
|
cpu_base = of_iomap(node, 1);
|
|
WARN(!cpu_base, "unable to map gic cpu registers\n");
|
|
|
|
if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
|
|
percpu_offset = 0;
|
|
|
|
gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
|
|
|
|
if (parent) {
|
|
irq = irq_of_parse_and_map(node, 0);
|
|
gic_cascade_irq(gic_cnt, irq);
|
|
}
|
|
gic_cnt++;
|
|
return 0;
|
|
}
|
|
IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
|
|
IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
|
|
IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
|
|
IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
|
|
|
|
#endif
|