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aa730cff0c
Move srso_alias_return_thunk() to the same section as srso_alias_safe_ret() so they can share a cache line. Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/eadaf5530b46a7ae8b936522da45ae555d2b3393.1693889988.git.jpoimboe@kernel.org
361 lines
9.3 KiB
ArmAsm
361 lines
9.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/stringify.h>
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#include <linux/linkage.h>
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#include <asm/dwarf2.h>
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#include <asm/cpufeatures.h>
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#include <asm/alternative.h>
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#include <asm/asm-offsets.h>
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#include <asm/export.h>
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#include <asm/nospec-branch.h>
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#include <asm/unwind_hints.h>
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#include <asm/percpu.h>
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#include <asm/frame.h>
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#include <asm/nops.h>
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.section .text..__x86.indirect_thunk
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.macro POLINE reg
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ANNOTATE_INTRA_FUNCTION_CALL
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call .Ldo_rop_\@
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int3
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.Ldo_rop_\@:
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mov %\reg, (%_ASM_SP)
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UNWIND_HINT_FUNC
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.endm
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.macro RETPOLINE reg
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POLINE \reg
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RET
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.endm
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.macro THUNK reg
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.align RETPOLINE_THUNK_SIZE
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SYM_INNER_LABEL(__x86_indirect_thunk_\reg, SYM_L_GLOBAL)
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UNWIND_HINT_UNDEFINED
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ANNOTATE_NOENDBR
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ALTERNATIVE_2 __stringify(RETPOLINE \reg), \
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__stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *%\reg; int3), X86_FEATURE_RETPOLINE_LFENCE, \
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__stringify(ANNOTATE_RETPOLINE_SAFE; jmp *%\reg), ALT_NOT(X86_FEATURE_RETPOLINE)
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.endm
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/*
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* Despite being an assembler file we can't just use .irp here
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* because __KSYM_DEPS__ only uses the C preprocessor and would
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* only see one instance of "__x86_indirect_thunk_\reg" rather
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* than one per register with the correct names. So we do it
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* the simple and nasty way...
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*
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* Worse, you can only have a single EXPORT_SYMBOL per line,
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* and CPP can't insert newlines, so we have to repeat everything
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* at least twice.
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*/
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#define __EXPORT_THUNK(sym) _ASM_NOKPROBE(sym); EXPORT_SYMBOL(sym)
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.align RETPOLINE_THUNK_SIZE
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SYM_CODE_START(__x86_indirect_thunk_array)
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#define GEN(reg) THUNK reg
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#include <asm/GEN-for-each-reg.h>
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#undef GEN
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.align RETPOLINE_THUNK_SIZE
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SYM_CODE_END(__x86_indirect_thunk_array)
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#define GEN(reg) __EXPORT_THUNK(__x86_indirect_thunk_ ## reg)
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#include <asm/GEN-for-each-reg.h>
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#undef GEN
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#ifdef CONFIG_CALL_DEPTH_TRACKING
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.macro CALL_THUNK reg
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.align RETPOLINE_THUNK_SIZE
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SYM_INNER_LABEL(__x86_indirect_call_thunk_\reg, SYM_L_GLOBAL)
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UNWIND_HINT_UNDEFINED
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ANNOTATE_NOENDBR
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CALL_DEPTH_ACCOUNT
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POLINE \reg
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ANNOTATE_UNRET_SAFE
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ret
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int3
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.endm
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.align RETPOLINE_THUNK_SIZE
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SYM_CODE_START(__x86_indirect_call_thunk_array)
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#define GEN(reg) CALL_THUNK reg
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#include <asm/GEN-for-each-reg.h>
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#undef GEN
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.align RETPOLINE_THUNK_SIZE
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SYM_CODE_END(__x86_indirect_call_thunk_array)
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#define GEN(reg) __EXPORT_THUNK(__x86_indirect_call_thunk_ ## reg)
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#include <asm/GEN-for-each-reg.h>
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#undef GEN
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.macro JUMP_THUNK reg
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.align RETPOLINE_THUNK_SIZE
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SYM_INNER_LABEL(__x86_indirect_jump_thunk_\reg, SYM_L_GLOBAL)
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UNWIND_HINT_UNDEFINED
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ANNOTATE_NOENDBR
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POLINE \reg
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ANNOTATE_UNRET_SAFE
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ret
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int3
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.endm
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.align RETPOLINE_THUNK_SIZE
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SYM_CODE_START(__x86_indirect_jump_thunk_array)
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#define GEN(reg) JUMP_THUNK reg
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#include <asm/GEN-for-each-reg.h>
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#undef GEN
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.align RETPOLINE_THUNK_SIZE
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SYM_CODE_END(__x86_indirect_jump_thunk_array)
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#define GEN(reg) __EXPORT_THUNK(__x86_indirect_jump_thunk_ ## reg)
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#include <asm/GEN-for-each-reg.h>
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#undef GEN
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#endif
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/*
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* This function name is magical and is used by -mfunction-return=thunk-extern
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* for the compiler to generate JMPs to it.
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*/
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#ifdef CONFIG_RETHUNK
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/*
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* srso_alias_untrain_ret() and srso_alias_safe_ret() are placed at
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* special addresses:
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*
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* - srso_alias_untrain_ret() is 2M aligned
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* - srso_alias_safe_ret() is also in the same 2M page but bits 2, 8, 14
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* and 20 in its virtual address are set (while those bits in the
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* srso_alias_untrain_ret() function are cleared).
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*
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* This guarantees that those two addresses will alias in the branch
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* target buffer of Zen3/4 generations, leading to any potential
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* poisoned entries at that BTB slot to get evicted.
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*
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* As a result, srso_alias_safe_ret() becomes a safe return.
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*/
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#ifdef CONFIG_CPU_SRSO
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.section .text..__x86.rethunk_untrain
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SYM_START(srso_alias_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
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UNWIND_HINT_FUNC
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ANNOTATE_NOENDBR
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ASM_NOP2
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lfence
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jmp srso_alias_return_thunk
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SYM_FUNC_END(srso_alias_untrain_ret)
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__EXPORT_THUNK(srso_alias_untrain_ret)
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.section .text..__x86.rethunk_safe
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#else
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/* dummy definition for alternatives */
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SYM_START(srso_alias_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
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ANNOTATE_UNRET_SAFE
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ret
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int3
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SYM_FUNC_END(srso_alias_untrain_ret)
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#endif
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SYM_START(srso_alias_safe_ret, SYM_L_GLOBAL, SYM_A_NONE)
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lea 8(%_ASM_SP), %_ASM_SP
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UNWIND_HINT_FUNC
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ANNOTATE_UNRET_SAFE
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ret
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int3
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SYM_FUNC_END(srso_alias_safe_ret)
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SYM_CODE_START_NOALIGN(srso_alias_return_thunk)
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UNWIND_HINT_FUNC
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ANNOTATE_NOENDBR
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call srso_alias_safe_ret
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ud2
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SYM_CODE_END(srso_alias_return_thunk)
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.section .text..__x86.return_thunk
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/*
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* Some generic notes on the untraining sequences:
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*
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* They are interchangeable when it comes to flushing potentially wrong
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* RET predictions from the BTB.
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*
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* The SRSO Zen1/2 (MOVABS) untraining sequence is longer than the
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* Retbleed sequence because the return sequence done there
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* (srso_safe_ret()) is longer and the return sequence must fully nest
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* (end before) the untraining sequence. Therefore, the untraining
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* sequence must fully overlap the return sequence.
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*
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* Regarding alignment - the instructions which need to be untrained,
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* must all start at a cacheline boundary for Zen1/2 generations. That
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* is, instruction sequences starting at srso_safe_ret() and
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* the respective instruction sequences at retbleed_return_thunk()
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* must start at a cacheline boundary.
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*/
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/*
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* Safety details here pertain to the AMD Zen{1,2} microarchitecture:
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* 1) The RET at retbleed_return_thunk must be on a 64 byte boundary, for
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* alignment within the BTB.
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* 2) The instruction at retbleed_untrain_ret must contain, and not
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* end with, the 0xc3 byte of the RET.
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* 3) STIBP must be enabled, or SMT disabled, to prevent the sibling thread
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* from re-poisioning the BTB prediction.
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*/
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.align 64
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.skip 64 - (retbleed_return_thunk - retbleed_untrain_ret), 0xcc
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SYM_START(retbleed_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
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ANNOTATE_NOENDBR
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/*
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* As executed from retbleed_untrain_ret, this is:
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*
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* TEST $0xcc, %bl
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* LFENCE
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* JMP retbleed_return_thunk
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*
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* Executing the TEST instruction has a side effect of evicting any BTB
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* prediction (potentially attacker controlled) attached to the RET, as
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* retbleed_return_thunk + 1 isn't an instruction boundary at the moment.
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*/
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.byte 0xf6
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/*
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* As executed from retbleed_return_thunk, this is a plain RET.
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*
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* As part of the TEST above, RET is the ModRM byte, and INT3 the imm8.
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*
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* We subsequently jump backwards and architecturally execute the RET.
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* This creates a correct BTB prediction (type=ret), but in the
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* meantime we suffer Straight Line Speculation (because the type was
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* no branch) which is halted by the INT3.
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*
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* With SMT enabled and STIBP active, a sibling thread cannot poison
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* RET's prediction to a type of its choice, but can evict the
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* prediction due to competitive sharing. If the prediction is
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* evicted, retbleed_return_thunk will suffer Straight Line Speculation
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* which will be contained safely by the INT3.
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*/
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SYM_INNER_LABEL(retbleed_return_thunk, SYM_L_GLOBAL)
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ret
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int3
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SYM_CODE_END(retbleed_return_thunk)
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/*
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* Ensure the TEST decoding / BTB invalidation is complete.
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*/
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lfence
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/*
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* Jump back and execute the RET in the middle of the TEST instruction.
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* INT3 is for SLS protection.
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*/
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jmp retbleed_return_thunk
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int3
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SYM_FUNC_END(retbleed_untrain_ret)
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__EXPORT_THUNK(retbleed_untrain_ret)
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/*
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* SRSO untraining sequence for Zen1/2, similar to retbleed_untrain_ret()
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* above. On kernel entry, srso_untrain_ret() is executed which is a
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*
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* movabs $0xccccc30824648d48,%rax
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*
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* and when the return thunk executes the inner label srso_safe_ret()
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* later, it is a stack manipulation and a RET which is mispredicted and
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* thus a "safe" one to use.
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*/
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.align 64
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.skip 64 - (srso_safe_ret - srso_untrain_ret), 0xcc
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SYM_START(srso_untrain_ret, SYM_L_GLOBAL, SYM_A_NONE)
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ANNOTATE_NOENDBR
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.byte 0x48, 0xb8
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/*
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* This forces the function return instruction to speculate into a trap
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* (UD2 in srso_return_thunk() below). This RET will then mispredict
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* and execution will continue at the return site read from the top of
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* the stack.
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*/
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SYM_INNER_LABEL(srso_safe_ret, SYM_L_GLOBAL)
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lea 8(%_ASM_SP), %_ASM_SP
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ret
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int3
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int3
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/* end of movabs */
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lfence
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call srso_safe_ret
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ud2
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SYM_CODE_END(srso_safe_ret)
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SYM_FUNC_END(srso_untrain_ret)
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__EXPORT_THUNK(srso_untrain_ret)
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SYM_CODE_START(srso_return_thunk)
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UNWIND_HINT_FUNC
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ANNOTATE_NOENDBR
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call srso_safe_ret
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ud2
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SYM_CODE_END(srso_return_thunk)
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SYM_FUNC_START(entry_untrain_ret)
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ALTERNATIVE_2 "jmp retbleed_untrain_ret", \
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"jmp srso_untrain_ret", X86_FEATURE_SRSO, \
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"jmp srso_alias_untrain_ret", X86_FEATURE_SRSO_ALIAS
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SYM_FUNC_END(entry_untrain_ret)
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__EXPORT_THUNK(entry_untrain_ret)
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SYM_CODE_START(__x86_return_thunk)
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UNWIND_HINT_FUNC
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ANNOTATE_NOENDBR
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ANNOTATE_UNRET_SAFE
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ret
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int3
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SYM_CODE_END(__x86_return_thunk)
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EXPORT_SYMBOL(__x86_return_thunk)
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#endif /* CONFIG_RETHUNK */
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#ifdef CONFIG_CALL_DEPTH_TRACKING
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.align 64
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SYM_FUNC_START(__x86_return_skl)
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ANNOTATE_NOENDBR
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/*
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* Keep the hotpath in a 16byte I-fetch for the non-debug
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* case.
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*/
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CALL_THUNKS_DEBUG_INC_RETS
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shlq $5, PER_CPU_VAR(pcpu_hot + X86_call_depth)
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jz 1f
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ANNOTATE_UNRET_SAFE
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ret
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int3
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1:
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CALL_THUNKS_DEBUG_INC_STUFFS
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.rept 16
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ANNOTATE_INTRA_FUNCTION_CALL
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call 2f
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int3
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2:
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.endr
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add $(8*16), %rsp
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CREDIT_CALL_DEPTH
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ANNOTATE_UNRET_SAFE
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ret
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int3
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SYM_FUNC_END(__x86_return_skl)
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#endif /* CONFIG_CALL_DEPTH_TRACKING */
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