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dd3cb467eb
As indicated in link: https://lore.kernel.org/all/20220822204945.GA808626-robh@kernel.org/ DT schema files should not have 'Device Tree Binding' as part of there title: line. Remove this in most .yaml files, so hopefully preventing developers copying it into new .yaml files, and being asked to remove it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220825020427.3460650-1-andrew@lunn.ch Signed-off-by: Rob Herring <robh@kernel.org>
121 lines
2.6 KiB
YAML
121 lines
2.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A80 Detail Enhancement Unit
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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description: |
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The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
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can sharpen the display content in both luma and chroma channels.
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properties:
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compatible:
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const: allwinner,sun9i-a80-deu
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: The DEU interface clock
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- description: The DEU module clock
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- description: The DEU DRAM clock
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clock-names:
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items:
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- const: ahb
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- const: mod
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- const: ram
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resets:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: |
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Input endpoints of the controller.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: |
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Output endpoints of the controller.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun9i-a80-de.h>
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#include <dt-bindings/reset/sun9i-a80-de.h>
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deu0: deu@3300000 {
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compatible = "allwinner,sun9i-a80-deu";
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reg = <0x03300000 0x40000>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&de_clocks CLK_BUS_DEU0>,
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<&de_clocks CLK_IEP_DEU0>,
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<&de_clocks CLK_DRAM_DEU0>;
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clock-names = "ahb",
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"mod",
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"ram";
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resets = <&de_clocks RST_DEU0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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deu0_in: port@0 {
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reg = <0>;
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deu0_in_fe0: endpoint {
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remote-endpoint = <&fe0_out_deu0>;
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};
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};
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deu0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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deu0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_deu0>;
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};
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deu0_out_be1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&be1_in_deu0>;
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};
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};
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};
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};
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...
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