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704cfd7f5f
The pen_release implementation was created for Versatile platforms to work around boot loaders that did not differentiate between the various different secondary CPUs on this ARM development platform. This should not be true of modern platforms where we send IPIs to specific CPUs to wake them up. Remove the pen_release stuff from SoCs that make use of the per-CPU IPI mechanism. The boot_lock is something that was required for ARM development platforms to ensure that the delay calibration worked properly. This is not necessary for modern platforms that have better bus bandwidth and do not need to calibrate the delay loop for secondary cores. Remove the boot_lock entirely. Due to pen_release and boot_lock removal, .smp_prepare_cpus and .smp_boot_secondary STi callbacks must be reworked properly to allow secondary CPU bring up. Secondary CPU is initialized and started by a U-BOOTROM firmware. Secondary CPU is spinning and waiting for a write at cpu_strt_ptr. Writing secondary_startup address at cpu_strt_ptr makes it to jump directly to secondary_startup(). This write must be done in .smp_boot_secondary callback and not in .smp_prepare_cpus as previously, this insures that secondary_data struct is populated in __cpu_up() (stack, pgdir and swapper_pg_dir fields). The IPI in sti_boot_secondary() is useless, so remove it. This patch is the merged of Russell's patch [1] and the rework of .smp_prepare_cpus and .smp_boot_secondary STi callbacks [2]. [1] https://patchwork.kernel.org/patch/10729435/ [2] https://patchwork.kernel.org/patch/10735795/ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
104 lines
2.3 KiB
C
104 lines
2.3 KiB
C
/*
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* arch/arm/mach-sti/platsmp.c
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*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* http://www.st.com
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*
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* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/memblock.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "smp.h"
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static u32 __iomem *cpu_strt_ptr;
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static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long entry_pa = __pa_symbol(secondary_startup);
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/*
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* Secondary CPU is initialised and started by a U-BOOTROM firmware.
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* Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.
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* Writing secondary_startup address at cpu_strt_ptr makes it to
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* jump directly to secondary_startup().
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*/
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__raw_writel(entry_pa, cpu_strt_ptr);
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/* wmb so that data is actually written before cache flush is done */
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smp_wmb();
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sync_cache_w(cpu_strt_ptr);
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return 0;
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}
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static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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void __iomem *scu_base;
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u32 release_phys;
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int cpu;
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (np) {
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scu_base = of_iomap(np, 0);
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scu_enable(scu_base);
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of_node_put(np);
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}
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if (max_cpus <= 1)
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return;
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for_each_possible_cpu(cpu) {
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np = of_get_cpu_node(cpu, NULL);
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if (!np)
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continue;
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if (of_property_read_u32(np, "cpu-release-addr",
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&release_phys)) {
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pr_err("CPU %d: missing or invalid cpu-release-addr "
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"property\n", cpu);
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continue;
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}
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/*
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* cpu-release-addr is usually configured in SBC DMEM but can
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* also be in RAM.
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*/
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if (!memblock_is_memory(release_phys))
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cpu_strt_ptr =
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ioremap(release_phys, sizeof(release_phys));
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else
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cpu_strt_ptr =
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(u32 __iomem *)phys_to_virt(release_phys);
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set_cpu_possible(cpu, true);
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}
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}
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const struct smp_operations sti_smp_ops __initconst = {
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.smp_prepare_cpus = sti_smp_prepare_cpus,
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.smp_boot_secondary = sti_boot_secondary,
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};
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