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Similar to MMP2, which this patch is based on. Known differencies from MMP2 are: * Two PJ4B cores instead of one PJ4 * Tauros 3 L2 cache controller instead of Tauros 2 * A GIC interrupt controller optionally used instead of the MMP one * A TWD local timer * Different USB2 PHY * A USB3 SS controller * More interrupt muxes Hard to tell what else is different, because documentation is not available. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
40 lines
1.2 KiB
Makefile
40 lines
1.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for Marvell's PXA168 processors line
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#
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ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-pxa/include
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obj-y += common.o devices.o time.o
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# SoC support
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obj-$(CONFIG_CPU_PXA168) += pxa168.o
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obj-$(CONFIG_CPU_PXA910) += pxa910.o
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obj-$(CONFIG_CPU_MMP2) += mmp2.o
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obj-$(CONFIG_MMP_SRAM) += sram.o
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ifeq ($(CONFIG_COMMON_CLK), )
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obj-y += clock.o
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obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o
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obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o
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obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o
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endif
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ifeq ($(CONFIG_PM),y)
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obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
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obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
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endif
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# board support
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obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
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obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
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obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
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obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
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obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
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obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
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obj-$(CONFIG_MACH_FLINT) += flint.o
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obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
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obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o
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obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o
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obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o
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obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
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obj-$(CONFIG_MACH_GPLUGD) += gplugd.o
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