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3370726042
The initial implementation in commit e120c17a70 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
181 lines
4.9 KiB
C
181 lines
4.9 KiB
C
/*
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* Marvell MV98DX3236 SoC clocks
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "common.h"
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/*
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* For 98DX4251 Sample At Reset the CPU, DDR and Main PLL clocks are all
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* defined at the same time
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*
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* SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
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* 0 = 400 MHz 400 MHz 800 MHz
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* 2 = 667 MHz 667 MHz 2000 MHz
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* 3 = 800 MHz 800 MHz 1600 MHz
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* others reserved.
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*
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* For 98DX3236 Sample At Reset the CPU, DDR and Main PLL clocks are all
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* defined at the same time
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*
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* SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
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* 1 = 667 MHz 667 MHz 2000 MHz
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* 2 = 400 MHz 400 MHz 400 MHz
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* 3 = 800 MHz 800 MHz 800 MHz
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* 5 = 800 MHz 400 MHz 800 MHz
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* others reserved.
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*/
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#define SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT 18
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#define SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK 0x7
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static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
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{
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/* Tclk = 200MHz, no SaR dependency */
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return 200000000;
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}
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static const u32 mv98dx3236_cpu_frequencies[] __initconst = {
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0,
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667000000,
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400000000,
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800000000,
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0,
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800000000,
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0, 0,
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};
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static const u32 mv98dx4251_cpu_frequencies[] __initconst = {
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400000000,
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0,
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667000000,
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800000000,
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0, 0, 0, 0,
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};
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static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
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{
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u32 cpu_freq = 0;
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u8 cpu_freq_select = 0;
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cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) &
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SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK);
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if (of_machine_is_compatible("marvell,armadaxp-98dx4251"))
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cpu_freq = mv98dx4251_cpu_frequencies[cpu_freq_select];
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else if (of_machine_is_compatible("marvell,armadaxp-98dx3236"))
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cpu_freq = mv98dx3236_cpu_frequencies[cpu_freq_select];
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if (!cpu_freq)
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pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
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return cpu_freq;
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}
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enum {
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MV98DX3236_CPU_TO_DDR,
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MV98DX3236_CPU_TO_MPLL
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};
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static const struct coreclk_ratio mv98dx3236_core_ratios[] __initconst = {
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{ .id = MV98DX3236_CPU_TO_DDR, .name = "ddrclk" },
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{ .id = MV98DX3236_CPU_TO_MPLL, .name = "mpll" },
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};
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static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
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{0, 1}, {3, 1}, {1, 1}, {1, 1},
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{0, 1}, {1, 1}, {0, 1}, {0, 1},
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};
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static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
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{0, 1}, {1, 1}, {1, 1}, {1, 1},
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{0, 1}, {1, 2}, {0, 1}, {0, 1},
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};
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static const int __initconst mv98dx4251_cpu_mpll_ratios[8][2] = {
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{2, 1}, {0, 1}, {3, 1}, {2, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static const int __initconst mv98dx4251_cpu_ddr_ratios[8][2] = {
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{1, 1}, {0, 1}, {1, 1}, {1, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static void __init mv98dx3236_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) &
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SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK);
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switch (id) {
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case MV98DX3236_CPU_TO_DDR:
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if (of_machine_is_compatible("marvell,armadaxp-98dx4251")) {
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*mult = mv98dx4251_cpu_ddr_ratios[opt][0];
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*div = mv98dx4251_cpu_ddr_ratios[opt][1];
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} else if (of_machine_is_compatible("marvell,armadaxp-98dx3236")) {
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*mult = mv98dx3236_cpu_ddr_ratios[opt][0];
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*div = mv98dx3236_cpu_ddr_ratios[opt][1];
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}
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break;
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case MV98DX3236_CPU_TO_MPLL:
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if (of_machine_is_compatible("marvell,armadaxp-98dx4251")) {
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*mult = mv98dx4251_cpu_mpll_ratios[opt][0];
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*div = mv98dx4251_cpu_mpll_ratios[opt][1];
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} else if (of_machine_is_compatible("marvell,armadaxp-98dx3236")) {
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*mult = mv98dx3236_cpu_mpll_ratios[opt][0];
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*div = mv98dx3236_cpu_mpll_ratios[opt][1];
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}
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break;
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}
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}
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static const struct coreclk_soc_desc mv98dx3236_core_clocks = {
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.get_tclk_freq = mv98dx3236_get_tclk_freq,
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.get_cpu_freq = mv98dx3236_get_cpu_freq,
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.get_clk_ratio = mv98dx3236_get_clk_ratio,
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.ratios = mv98dx3236_core_ratios,
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.num_ratios = ARRAY_SIZE(mv98dx3236_core_ratios),
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};
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/*
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* Clock Gating Control
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*/
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static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
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{ "ge1", NULL, 3, 0 },
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{ "ge0", NULL, 4, 0 },
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{ "pex00", NULL, 5, 0 },
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{ "sdio", NULL, 17, 0 },
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{ "usb0", NULL, 18, 0 },
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{ "xor0", NULL, 22, 0 },
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{ }
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};
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static void __init mv98dx3236_clk_init(struct device_node *np)
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{
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struct device_node *cgnp =
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of_find_compatible_node(NULL, NULL, "marvell,mv98dx3236-gating-clock");
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mvebu_coreclk_setup(np, &mv98dx3236_core_clocks);
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if (cgnp)
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mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
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}
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CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock", mv98dx3236_clk_init);
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