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a8d46a7f5d
DMAC reads data from source device, and buffered it until transferable size for sink device. Because of this behavior, DMAC is including buffered data . Now, CHCR DE bit is controlling DMA transfer enable/disable. If DE bit was cleared during data transferring, or during buffering, it will flush buffered data if source device was peripheral device (The buffered data will be removed if source device was memory). Because of this behavior, driver should ensure that DE bit is actually 0 after clearing. This patch adds new rcar_dmac_chcr_de_barrier() and call it after CHCR register access. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Tested-by: Ryo Kodama <ryo.kodama.vz@renesas.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| rcar-dmac.c | ||
| shdma-arm.h | ||
| shdma-base.c | ||
| shdma-of.c | ||
| shdma-r8a73a4.c | ||
| shdma.h | ||
| shdmac.c | ||
| sudmac.c | ||
| usb-dmac.c | ||