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As we have one to three pinctrl-single instances for each SoC it is a bit confusing to configure the padconf register offset from the base of the padconf register base. Let's add macros that allow using the physical address of the padconf register directly, or in most cases, just the last 16-bits of the address as they are shown in the documentation. Note that most documentation shows two padconf registers for each 32-bit address, so adding 2 to the documentation address is needed for the second padconf register as we treat them as 16-bit registers for omap3+. For example, omap36xx documentation shows sdmmc2_clk at 0x48002158, so we can just use the last 16-bits of that value: pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) ... >; And we don't need to separately calculate the offset from the 0x2030 base: pinctrl-single,pins = < 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) ... >; Naturally both ways of defining the registers can be used, and I'm not saying we should replace all the existing defines. But it may be handy to use these macros for new entries and when doing other related .dts file clean-up. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> [tony@atomide.com: updated for 3430 vs 3630 core2 range] Signed-off-by: Tony Lindgren <tony@atomide.com>
74 lines
2.5 KiB
C
74 lines
2.5 KiB
C
/*
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* This header provides constants for OMAP pinctrl bindings.
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*
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* Copyright (C) 2009 Nokia
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* Copyright (C) 2009-2010 Texas Instruments
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*/
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#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
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#define _DT_BINDINGS_PINCTRL_OMAP_H
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/* 34xx mux mode options for each pin. See TRM for options */
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#define MUX_MODE0 0
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#define MUX_MODE1 1
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#define MUX_MODE2 2
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#define MUX_MODE3 3
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#define MUX_MODE4 4
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#define MUX_MODE5 5
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#define MUX_MODE6 6
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#define MUX_MODE7 7
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/* 24xx/34xx mux bit defines */
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#define PULL_ENA (1 << 3)
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#define PULL_UP (1 << 4)
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#define ALTELECTRICALSEL (1 << 5)
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/* omap3/4/5 specific mux bit defines */
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#define INPUT_EN (1 << 8)
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#define OFF_EN (1 << 9)
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#define OFFOUT_EN (1 << 10)
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#define OFFOUT_VAL (1 << 11)
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#define OFF_PULL_EN (1 << 12)
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#define OFF_PULL_UP (1 << 13)
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#define WAKEUP_EN (1 << 14)
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#define WAKEUP_EVENT (1 << 15)
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/* Active pin states */
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#define PIN_OUTPUT 0
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#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
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#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
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#define PIN_INPUT INPUT_EN
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#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
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#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
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/* Off mode states */
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#define PIN_OFF_NONE 0
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#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
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#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
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#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
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#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
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#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
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/*
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* Macros to allow using the absolute physical address instead of the
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* padconf registers instead of the offset from padconf base.
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*/
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#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
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#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
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#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
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#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
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#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
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#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
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#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
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#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
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#define OMAP4_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0040) (val)
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#define OMAP4_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xe040) (val)
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#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
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#define OMAP5_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2840) (val)
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#define OMAP5_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xc840) (val)
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#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
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#endif
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