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35d33c76d6
Because of the stack canary feature that reads from the current task
structure the stack canary value, the thread pointer register "tp" must
be set before calling any C function from head.S: by chance, setup_vm
and all the functions that it calls does not seem to be part of the
functions where the canary check is done, but in the following commits,
some functions will.
Fixes: f2c9699f65 ("riscv: Add STACKPROTECTOR supported")
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
438 lines
8.8 KiB
ArmAsm
438 lines
8.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#include <asm/asm-offsets.h>
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#include <asm/asm.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/csr.h>
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#include <asm/cpu_ops_sbi.h>
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#include <asm/hwcap.h>
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#include <asm/image.h>
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#include <asm/xip_fixup.h>
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#include "efi-header.S"
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__HEAD
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ENTRY(_start)
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/*
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* Image header expected by Linux boot-loaders. The image header data
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* structure is described in asm/image.h.
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* Do not modify it without modifying the structure and all bootloaders
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* that expects this header format!!
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*/
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#ifdef CONFIG_EFI
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/*
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* This instruction decodes to "MZ" ASCII required by UEFI.
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*/
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c.li s4,-13
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j _start_kernel
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#else
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/* jump to start kernel */
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j _start_kernel
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/* reserved */
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.word 0
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#endif
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.balign 8
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#ifdef CONFIG_RISCV_M_MODE
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/* Image load offset (0MB) from start of RAM for M-mode */
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.dword 0
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#else
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#if __riscv_xlen == 64
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/* Image load offset(2MB) from start of RAM */
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.dword 0x200000
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#else
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/* Image load offset(4MB) from start of RAM */
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.dword 0x400000
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#endif
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#endif
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/* Effective size of kernel image */
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.dword _end - _start
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.dword __HEAD_FLAGS
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.word RISCV_HEADER_VERSION
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.word 0
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.dword 0
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.ascii RISCV_IMAGE_MAGIC
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.balign 4
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.ascii RISCV_IMAGE_MAGIC2
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#ifdef CONFIG_EFI
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.word pe_head_start - _start
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pe_head_start:
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__EFI_PE_HEADER
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#else
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.word 0
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#endif
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.align 2
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#ifdef CONFIG_MMU
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.global relocate_enable_mmu
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relocate_enable_mmu:
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/* Relocate return address */
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la a1, kernel_map
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XIP_FIXUP_OFFSET a1
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REG_L a1, KERNEL_MAP_VIRT_ADDR(a1)
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la a2, _start
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sub a1, a1, a2
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add ra, ra, a1
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/* Point stvec to virtual address of intruction after satp write */
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la a2, 1f
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add a2, a2, a1
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csrw CSR_TVEC, a2
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/* Compute satp for kernel page tables, but don't load it yet */
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srl a2, a0, PAGE_SHIFT
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la a1, satp_mode
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REG_L a1, 0(a1)
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or a2, a2, a1
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/*
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* Load trampoline page directory, which will cause us to trap to
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* stvec if VA != PA, or simply fall through if VA == PA. We need a
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* full fence here because setup_vm() just wrote these PTEs and we need
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* to ensure the new translations are in use.
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*/
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la a0, trampoline_pg_dir
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XIP_FIXUP_OFFSET a0
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srl a0, a0, PAGE_SHIFT
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or a0, a0, a1
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sfence.vma
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csrw CSR_SATP, a0
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.align 2
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1:
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/* Set trap vector to spin forever to help debug */
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la a0, .Lsecondary_park
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csrw CSR_TVEC, a0
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/* Reload the global pointer */
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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/*
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* Switch to kernel page tables. A full fence is necessary in order to
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* avoid using the trampoline translations, which are only correct for
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* the first superpage. Fetching the fence is guaranteed to work
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* because that first superpage is translated the same way.
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*/
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csrw CSR_SATP, a2
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sfence.vma
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ret
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#endif /* CONFIG_MMU */
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#ifdef CONFIG_SMP
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.global secondary_start_sbi
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secondary_start_sbi:
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/* Mask all interrupts */
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csrw CSR_IE, zero
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csrw CSR_IP, zero
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/* Load the global pointer */
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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/*
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* Disable FPU to detect illegal usage of
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* floating point in kernel space
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*/
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li t0, SR_FS
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csrc CSR_STATUS, t0
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/* Set trap vector to spin forever to help debug */
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la a3, .Lsecondary_park
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csrw CSR_TVEC, a3
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/* a0 contains the hartid & a1 contains boot data */
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li a2, SBI_HART_BOOT_TASK_PTR_OFFSET
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XIP_FIXUP_OFFSET a2
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add a2, a2, a1
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REG_L tp, (a2)
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li a3, SBI_HART_BOOT_STACK_PTR_OFFSET
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XIP_FIXUP_OFFSET a3
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add a3, a3, a1
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REG_L sp, (a3)
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.Lsecondary_start_common:
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#ifdef CONFIG_MMU
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/* Enable virtual memory and relocate to virtual address */
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la a0, swapper_pg_dir
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XIP_FIXUP_OFFSET a0
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call relocate_enable_mmu
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#endif
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call setup_trap_vector
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tail smp_callin
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#endif /* CONFIG_SMP */
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.align 2
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setup_trap_vector:
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/* Set trap vector to exception handler */
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la a0, handle_exception
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csrw CSR_TVEC, a0
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/*
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* Set sup0 scratch register to 0, indicating to exception vector that
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* we are presently executing in kernel.
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*/
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csrw CSR_SCRATCH, zero
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ret
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.align 2
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.Lsecondary_park:
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/* We lack SMP support or have too many harts, so park this hart */
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wfi
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j .Lsecondary_park
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END(_start)
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ENTRY(_start_kernel)
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/* Mask all interrupts */
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csrw CSR_IE, zero
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csrw CSR_IP, zero
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#ifdef CONFIG_RISCV_M_MODE
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/* flush the instruction cache */
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fence.i
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/* Reset all registers except ra, a0, a1 */
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call reset_regs
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/*
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* Setup a PMP to permit access to all of memory. Some machines may
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* not implement PMPs, so we set up a quick trap handler to just skip
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* touching the PMPs on any trap.
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*/
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la a0, pmp_done
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csrw CSR_TVEC, a0
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li a0, -1
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csrw CSR_PMPADDR0, a0
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li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
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csrw CSR_PMPCFG0, a0
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.align 2
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pmp_done:
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/*
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* The hartid in a0 is expected later on, and we have no firmware
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* to hand it to us.
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*/
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csrr a0, CSR_MHARTID
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#endif /* CONFIG_RISCV_M_MODE */
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/* Load the global pointer */
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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/*
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* Disable FPU to detect illegal usage of
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* floating point in kernel space
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*/
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li t0, SR_FS
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csrc CSR_STATUS, t0
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#ifdef CONFIG_RISCV_BOOT_SPINWAIT
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li t0, CONFIG_NR_CPUS
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blt a0, t0, .Lgood_cores
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tail .Lsecondary_park
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.Lgood_cores:
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/* The lottery system is only required for spinwait booting method */
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#ifndef CONFIG_XIP_KERNEL
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/* Pick one hart to run the main boot sequence */
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la a3, hart_lottery
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li a2, 1
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amoadd.w a3, a2, (a3)
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bnez a3, .Lsecondary_start
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#else
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/* hart_lottery in flash contains a magic number */
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la a3, hart_lottery
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mv a2, a3
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XIP_FIXUP_OFFSET a2
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XIP_FIXUP_FLASH_OFFSET a3
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lw t1, (a3)
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amoswap.w t0, t1, (a2)
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/* first time here if hart_lottery in RAM is not set */
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beq t0, t1, .Lsecondary_start
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#endif /* CONFIG_XIP */
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#endif /* CONFIG_RISCV_BOOT_SPINWAIT */
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#ifdef CONFIG_XIP_KERNEL
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la sp, _end + THREAD_SIZE
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XIP_FIXUP_OFFSET sp
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mv s0, a0
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call __copy_data
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/* Restore a0 copy */
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mv a0, s0
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#endif
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#ifndef CONFIG_XIP_KERNEL
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/* Clear BSS for flat non-ELF images */
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la a3, __bss_start
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la a4, __bss_stop
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ble a4, a3, clear_bss_done
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clear_bss:
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REG_S zero, (a3)
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add a3, a3, RISCV_SZPTR
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blt a3, a4, clear_bss
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clear_bss_done:
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#endif
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/* Save hart ID and DTB physical address */
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mv s0, a0
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mv s1, a1
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la a2, boot_cpu_hartid
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XIP_FIXUP_OFFSET a2
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REG_S a0, (a2)
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/* Initialize page tables and relocate to virtual addresses */
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la tp, init_task
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la sp, init_thread_union + THREAD_SIZE
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XIP_FIXUP_OFFSET sp
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#ifdef CONFIG_BUILTIN_DTB
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la a0, __dtb_start
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XIP_FIXUP_OFFSET a0
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#else
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mv a0, s1
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#endif /* CONFIG_BUILTIN_DTB */
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call setup_vm
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#ifdef CONFIG_MMU
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la a0, early_pg_dir
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XIP_FIXUP_OFFSET a0
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call relocate_enable_mmu
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#endif /* CONFIG_MMU */
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call setup_trap_vector
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/* Restore C environment */
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la tp, init_task
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la sp, init_thread_union + THREAD_SIZE
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#ifdef CONFIG_KASAN
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call kasan_early_init
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#endif
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/* Start the kernel */
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call soc_early_init
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tail start_kernel
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#if CONFIG_RISCV_BOOT_SPINWAIT
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.Lsecondary_start:
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/* Set trap vector to spin forever to help debug */
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la a3, .Lsecondary_park
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csrw CSR_TVEC, a3
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slli a3, a0, LGREG
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la a1, __cpu_spinwait_stack_pointer
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XIP_FIXUP_OFFSET a1
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la a2, __cpu_spinwait_task_pointer
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XIP_FIXUP_OFFSET a2
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add a1, a3, a1
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add a2, a3, a2
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/*
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* This hart didn't win the lottery, so we wait for the winning hart to
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* get far enough along the boot process that it should continue.
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*/
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.Lwait_for_cpu_up:
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/* FIXME: We should WFI to save some energy here. */
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REG_L sp, (a1)
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REG_L tp, (a2)
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beqz sp, .Lwait_for_cpu_up
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beqz tp, .Lwait_for_cpu_up
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fence
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tail .Lsecondary_start_common
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#endif /* CONFIG_RISCV_BOOT_SPINWAIT */
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END(_start_kernel)
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#ifdef CONFIG_RISCV_M_MODE
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ENTRY(reset_regs)
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li sp, 0
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li gp, 0
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li tp, 0
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li t0, 0
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li t1, 0
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li t2, 0
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li s0, 0
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li s1, 0
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li a2, 0
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li a3, 0
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li a4, 0
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li a5, 0
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li a6, 0
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li a7, 0
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li s2, 0
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li s3, 0
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li s4, 0
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li s5, 0
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li s6, 0
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li s7, 0
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li s8, 0
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li s9, 0
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li s10, 0
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li s11, 0
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li t3, 0
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li t4, 0
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li t5, 0
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li t6, 0
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csrw CSR_SCRATCH, 0
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#ifdef CONFIG_FPU
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csrr t0, CSR_MISA
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andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
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beqz t0, .Lreset_regs_done
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li t1, SR_FS
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csrs CSR_STATUS, t1
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fmv.s.x f0, zero
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fmv.s.x f1, zero
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fmv.s.x f2, zero
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fmv.s.x f3, zero
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fmv.s.x f4, zero
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fmv.s.x f5, zero
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fmv.s.x f6, zero
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fmv.s.x f7, zero
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fmv.s.x f8, zero
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fmv.s.x f9, zero
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fmv.s.x f10, zero
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fmv.s.x f11, zero
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fmv.s.x f12, zero
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fmv.s.x f13, zero
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fmv.s.x f14, zero
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fmv.s.x f15, zero
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fmv.s.x f16, zero
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fmv.s.x f17, zero
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fmv.s.x f18, zero
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fmv.s.x f19, zero
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fmv.s.x f20, zero
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fmv.s.x f21, zero
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fmv.s.x f22, zero
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fmv.s.x f23, zero
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fmv.s.x f24, zero
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fmv.s.x f25, zero
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fmv.s.x f26, zero
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fmv.s.x f27, zero
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fmv.s.x f28, zero
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fmv.s.x f29, zero
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fmv.s.x f30, zero
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fmv.s.x f31, zero
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csrw fcsr, 0
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/* note that the caller must clear SR_FS */
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#endif /* CONFIG_FPU */
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.Lreset_regs_done:
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ret
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END(reset_regs)
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#endif /* CONFIG_RISCV_M_MODE */
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