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86e78995c9
While fixing up the driver I noticed that my IPQ8074 board was hanging
after CPUFreq switched the frequency during boot, WDT would eventually
reset it.
So mark apcs_alias0_core_clk as critical since its the clock feeding the
CPU cluster and must never be disabled.
Fixes: 5e77b4ef1b ("clk: qcom: Add ipq6018 apss clock controller")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220818220628.339366-3-robimarko@gmail.com
106 lines
2.5 KiB
C
106 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-branch.h"
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#include "clk-alpha-pll.h"
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#include "clk-rcg.h"
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enum {
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P_XO,
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P_APSS_PLL_EARLY,
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};
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static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
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{ .fw_name = "xo" },
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{ .fw_name = "pll" },
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};
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static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
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{ P_XO, 0 },
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{ P_APSS_PLL_EARLY, 5 },
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};
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static struct clk_rcg2 apcs_alias0_clk_src = {
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.cmd_rcgr = 0x0050,
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.hid_width = 5,
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.parent_map = parents_apcs_alias0_clk_src_map,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "apcs_alias0_clk_src",
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.parent_data = parents_apcs_alias0_clk_src,
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.num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
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.ops = &clk_rcg2_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_branch apcs_alias0_core_clk = {
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.halt_reg = 0x0058,
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.clkr = {
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.enable_reg = 0x0058,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "apcs_alias0_core_clk",
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.parent_hws = (const struct clk_hw *[]){
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&apcs_alias0_clk_src.clkr.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static const struct regmap_config apss_ipq6018_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x1000,
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.fast_io = true,
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};
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static struct clk_regmap *apss_ipq6018_clks[] = {
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[APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr,
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[APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr,
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};
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static const struct qcom_cc_desc apss_ipq6018_desc = {
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.config = &apss_ipq6018_regmap_config,
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.clks = apss_ipq6018_clks,
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.num_clks = ARRAY_SIZE(apss_ipq6018_clks),
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};
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static int apss_ipq6018_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!regmap)
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return -ENODEV;
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return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
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}
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static struct platform_driver apss_ipq6018_driver = {
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.probe = apss_ipq6018_probe,
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.driver = {
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.name = "qcom,apss-ipq6018-clk",
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},
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};
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module_platform_driver(apss_ipq6018_driver);
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MODULE_DESCRIPTION("QCOM APSS IPQ 6018 CLK Driver");
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MODULE_LICENSE("GPL v2");
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