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b2d4383480
Choose PAGE_OFFSET dynamically based upon cpu type. Original UltraSPARC-I (spitfire) chips only supported a 44-bit virtual address space. Newer chips (T4 and later) support 52-bit virtual addresses and up to 47-bits of physical memory space. Therefore we have to adjust PAGE_SIZE dynamically based upon the capabilities of the chip. Note that this change alone does not allow us to support > 43-bit physical memory, to do that we need to re-arrange our page table support. The current encodings of the pmd_t and pgd_t pointers restricts us to "32 + 11" == 43 bits. This change can waste quite a bit of memory for the various tables. In particular, a future change should work to size and allocate kern_linear_bitmap[] and sparc64_valid_addr_bitmap[] dynamically. This isn't easy as we really cannot take a TLB miss when accessing kern_linear_bitmap[]. We'd have to lock it into the TLB or similar. Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Bob Picco <bob.picco@oracle.com>
157 lines
2.9 KiB
ArmAsm
157 lines
2.9 KiB
ArmAsm
/* ld script for sparc32/sparc64 kernel */
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#include <asm-generic/vmlinux.lds.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#ifdef CONFIG_SPARC32
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#define INITIAL_ADDRESS 0x10000 + SIZEOF_HEADERS
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#define TEXTSTART 0xf0004000
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#define SMP_CACHE_BYTES_SHIFT 5
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#else
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#define SMP_CACHE_BYTES_SHIFT 6
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#define INITIAL_ADDRESS 0x4000
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#define TEXTSTART 0x0000000000404000
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#endif
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#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
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#ifdef CONFIG_SPARC32
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OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
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OUTPUT_ARCH(sparc)
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ENTRY(_start)
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jiffies = jiffies_64 + 4;
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#else
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/* sparc64 */
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OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "elf64-sparc")
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OUTPUT_ARCH(sparc:v9a)
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ENTRY(_start)
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jiffies = jiffies_64;
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#endif
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SECTIONS
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{
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/* swapper_low_pmd_dir is sparc64 only */
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swapper_low_pmd_dir = 0x0000000000402000;
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. = INITIAL_ADDRESS;
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.text TEXTSTART :
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{
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_text = .;
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HEAD_TEXT
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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IRQENTRY_TEXT
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*(.gnu.warning)
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} = 0
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_etext = .;
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RO_DATA(PAGE_SIZE)
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/* Start of data section */
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_sdata = .;
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.data1 : {
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*(.data1)
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}
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RW_DATA_SECTION(SMP_CACHE_BYTES, 0, THREAD_SIZE)
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/* End of data section */
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_edata = .;
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.fixup : {
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__start___fixup = .;
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*(.fixup)
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__stop___fixup = .;
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}
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EXCEPTION_TABLE(16)
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NOTES
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. = ALIGN(PAGE_SIZE);
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__init_begin = ALIGN(PAGE_SIZE);
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INIT_TEXT_SECTION(PAGE_SIZE)
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__init_text_end = .;
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INIT_DATA_SECTION(16)
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. = ALIGN(4);
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.tsb_ldquad_phys_patch : {
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__tsb_ldquad_phys_patch = .;
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*(.tsb_ldquad_phys_patch)
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__tsb_ldquad_phys_patch_end = .;
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}
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.tsb_phys_patch : {
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__tsb_phys_patch = .;
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*(.tsb_phys_patch)
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__tsb_phys_patch_end = .;
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}
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.cpuid_patch : {
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__cpuid_patch = .;
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*(.cpuid_patch)
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__cpuid_patch_end = .;
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}
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.sun4v_1insn_patch : {
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__sun4v_1insn_patch = .;
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*(.sun4v_1insn_patch)
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__sun4v_1insn_patch_end = .;
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}
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.sun4v_2insn_patch : {
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__sun4v_2insn_patch = .;
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*(.sun4v_2insn_patch)
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__sun4v_2insn_patch_end = .;
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}
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.leon_1insn_patch : {
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__leon_1insn_patch = .;
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*(.leon_1insn_patch)
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__leon_1insn_patch_end = .;
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}
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.swapper_tsb_phys_patch : {
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__swapper_tsb_phys_patch = .;
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*(.swapper_tsb_phys_patch)
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__swapper_tsb_phys_patch_end = .;
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}
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.swapper_4m_tsb_phys_patch : {
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__swapper_4m_tsb_phys_patch = .;
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*(.swapper_4m_tsb_phys_patch)
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__swapper_4m_tsb_phys_patch_end = .;
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}
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.page_offset_shift_patch : {
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__page_offset_shift_patch = .;
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*(.page_offset_shift_patch)
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__page_offset_shift_patch_end = .;
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}
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.popc_3insn_patch : {
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__popc_3insn_patch = .;
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*(.popc_3insn_patch)
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__popc_3insn_patch_end = .;
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}
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.popc_6insn_patch : {
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__popc_6insn_patch = .;
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*(.popc_6insn_patch)
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__popc_6insn_patch_end = .;
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}
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.pause_3insn_patch : {
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__pause_3insn_patch = .;
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*(.pause_3insn_patch)
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__pause_3insn_patch_end = .;
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}
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PERCPU_SECTION(SMP_CACHE_BYTES)
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. = ALIGN(PAGE_SIZE);
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__init_end = .;
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BSS_SECTION(0, 0, 0)
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_end = . ;
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STABS_DEBUG
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DWARF_DEBUG
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DISCARDS
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}
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