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The commita9ddb575d6("dmaengine: dw_dmac: Enhance device tree support") introduces is_private property in uncertain understanding what does it mean. First of all, documentation defines DMA_PRIVATE capability as Documentation/crypto/async-tx-api.txt: The DMA_PRIVATE capability flag is used to tag dma devices that should not be used by the general-purpose allocator. It can be set at initialization time if it is known that a channel will always be private. Alternatively, it is set when dma_request_channel() finds an unused "public" channel. A couple caveats to note when implementing a driver and consumer: 1/ Once a channel has been privately allocated it will no longer be considered by the general-purpose allocator even after a call to dma_release_channel(). 2/ Since capabilities are specified at the device level a dma_device with multiple channels will either have all channels public, or all channels private. Documentation/driver-api/dmaengine/provider.rst: - DMA_PRIVATE The devices only supports slave transfers, and as such isn't available for async transfers. The capability had been introduced by the commit59b5ec2144("dmaengine: introduce dma_request_channel and private channels") and some code didn't changed from that times ever. Taking into consideration above and the fact that on all known platforms Synopsys DesignWare DMA engine is attached to serve slave transfers, the DMA_PRIVATE capability must be enabled for this device unconditionally. Otherwise, as rightfully noticed in drivers/dma/at_xdmac.c: /* * Without DMA_PRIVATE the driver is not able to allocate more than * one channel, second allocation fails in private_candidate. */ because of of a caveats mentioned in above documentation excerpts. So, remove conditional around DMA_PRIVATE followed by removal leftovers. If someone wonders, DMA_PRIVATE can be not used if and only if the all channels of the DMA controller are supposed to serve memory-to-memory like operations. For example, EP93xx has two controllers, one of which can only perform memory-to-memory transfers Note, this change doesn't affect dmatest to be able to test such controllers. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (maintainer:SERIAL DRIVERS) Cc: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
70 lines
2.2 KiB
Plaintext
70 lines
2.2 KiB
Plaintext
* Synopsys Designware DMA Controller
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Required properties:
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- compatible: "snps,dma-spear1340"
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- reg: Address range of the DMAC registers
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- interrupt: Should contain the DMAC interrupt number
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- dma-channels: Number of channels supported by hardware
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- dma-requests: Number of DMA request lines supported, up to 16
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- dma-masters: Number of AHB masters supported by the controller
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- #dma-cells: must be <3>
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- chan_allocation_order: order of allocation of channel, 0 (default): ascending,
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1: descending
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- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
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increase from chan n->0
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- block_size: Maximum block size supported by the controller
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- data-width: Maximum data width supported by hardware per AHB master
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(in bytes, power of 2)
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Deprecated properties:
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- data_width: Maximum data width supported by hardware per AHB master
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(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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Optional properties:
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- multi-block: Multi block transfers supported by hardware. Array property with
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one cell per channel. 0: not supported, 1 (default): supported.
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- snps,dma-protection-control: AHB HPROT[3:1] protection setting.
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The default value is 0 (for non-cacheable, non-buffered,
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unprivileged data access).
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Refer to include/dt-bindings/dma/dw-dmac.h for possible values.
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Example:
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dmahost: dma@fc000000 {
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compatible = "snps,dma-spear1340";
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reg = <0xfc000000 0x1000>;
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interrupt-parent = <&vic1>;
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interrupts = <12>;
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dma-channels = <8>;
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dma-requests = <16>;
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dma-masters = <2>;
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#dma-cells = <3>;
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chan_allocation_order = <1>;
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chan_priority = <1>;
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block_size = <0xfff>;
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data-width = <8 8>;
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};
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DMA clients connected to the Designware DMA controller must use the format
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described in the dma.txt file, using a four-cell specifier for each channel.
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The four cells in order are:
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1. A phandle pointing to the DMA controller
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2. The DMA request line number
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3. Memory master for transfers on allocated channel
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4. Peripheral master for transfers on allocated channel
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Example:
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serial@e0000000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xe0000000 0x1000>;
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interrupts = <0 35 0x4>;
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dmas = <&dmahost 12 0 1>,
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<&dmahost 13 1 0>;
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dma-names = "rx", "rx";
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};
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