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a50371f2ef
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty until the child devices are probing with ti-sysc interconnect driver. Initially let's just update the top level dss node to probe with ti-sysc interconnect target module driver. The child nodes are still children of dispc, only the node indentation changes for them now along with using the reg range provided by top level dss. Cc: Jyri Sarha <jsarha@ti.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
186 lines
4.2 KiB
Plaintext
186 lines
4.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on "omap4.dtsi"
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*/
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#include "dra7.dtsi"
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/ {
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compatible = "ti,dra742", "ti,dra74", "ti,dra7";
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cpus {
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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operating-points-v2 = <&cpu0_opp_table>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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/* cooling options */
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#cooling-cells = <2>; /* min followed by max */
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vbb-supply = <&abb_mpu>;
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};
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupt-parent = <&wakeupgen>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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};
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ocp {
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dsp2_system: dsp_system@41500000 {
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compatible = "syscon";
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reg = <0x41500000 0x100>;
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};
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omap_dwc3_4: omap_dwc3_4@48940000 {
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compatible = "ti,dwc3";
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ti,hwmods = "usb_otg_ss4";
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reg = <0x48940000 0x10000>;
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interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <1>;
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utmi-mode = <2>;
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ranges;
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status = "disabled";
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usb4: usb@48950000 {
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compatible = "snps,dwc3";
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reg = <0x48950000 0x17000>;
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interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "peripheral",
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"host",
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"otg";
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maximum-speed = "high-speed";
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dr_mode = "otg";
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};
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};
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target-module@41501000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x41501000 0x4>,
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<0x41501010 0x4>,
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<0x41501014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
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clock-names = "fck";
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resets = <&prm_dsp2 1>;
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reset-names = "rstctrl";
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ranges = <0x0 0x41501000 0x1000>;
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#size-cells = <1>;
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#address-cells = <1>;
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mmu0_dsp2: mmu@0 {
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compatible = "ti,dra7-dsp-iommu";
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reg = <0x0 0x100>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <0>;
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ti,syscon-mmuconfig = <&dsp2_system 0x0>;
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};
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};
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target-module@41502000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x41502000 0x4>,
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<0x41502010 0x4>,
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<0x41502014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
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clock-names = "fck";
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resets = <&prm_dsp2 1>;
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reset-names = "rstctrl";
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ranges = <0x0 0x41502000 0x1000>;
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#size-cells = <1>;
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#address-cells = <1>;
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mmu1_dsp2: mmu@0 {
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compatible = "ti,dra7-dsp-iommu";
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reg = <0x0 0x100>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <0>;
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ti,syscon-mmuconfig = <&dsp2_system 0x1>;
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};
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};
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};
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};
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&cpu0_opp_table {
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opp-shared;
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};
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&dss {
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reg = <0 0x80>,
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<0x4054 0x4>,
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<0x4300 0x20>,
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<0x9054 0x4>,
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<0x9300 0x20>;
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reg-names = "dss", "pll1_clkctrl", "pll1",
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"pll2_clkctrl", "pll2";
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clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
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<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
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<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
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clock-names = "fck", "video1_clk", "video2_clk";
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};
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&mailbox5 {
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mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
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ti,mbox-tx = <6 2 2>;
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ti,mbox-rx = <4 2 2>;
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status = "disabled";
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};
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mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
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ti,mbox-tx = <5 2 2>;
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ti,mbox-rx = <1 2 2>;
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status = "disabled";
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};
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};
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&mailbox6 {
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mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
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ti,mbox-tx = <6 2 2>;
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ti,mbox-rx = <4 2 2>;
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status = "disabled";
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};
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mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
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ti,mbox-tx = <5 2 2>;
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ti,mbox-rx = <1 2 2>;
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status = "disabled";
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};
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};
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&pcie1_rc {
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compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
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};
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&pcie1_ep {
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compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
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};
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&pcie2_rc {
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compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
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};
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