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9f5890466e
Change legacy name master to modern name host. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230728093221.3312026-21-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
554 lines
14 KiB
C
554 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// HiSilicon SPI Controller Driver for Kunpeng SoCs
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//
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// Copyright (c) 2021 HiSilicon Technologies Co., Ltd.
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// Author: Jay Fang <f.fangjian@huawei.com>
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//
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// This code is based on spi-dw-core.c.
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#include <linux/acpi.h>
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#include <linux/bitfield.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/property.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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/* Register offsets */
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#define HISI_SPI_CSCR 0x00 /* cs control register */
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#define HISI_SPI_CR 0x04 /* spi common control register */
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#define HISI_SPI_ENR 0x08 /* spi enable register */
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#define HISI_SPI_FIFOC 0x0c /* fifo level control register */
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#define HISI_SPI_IMR 0x10 /* interrupt mask register */
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#define HISI_SPI_DIN 0x14 /* data in register */
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#define HISI_SPI_DOUT 0x18 /* data out register */
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#define HISI_SPI_SR 0x1c /* status register */
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#define HISI_SPI_RISR 0x20 /* raw interrupt status register */
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#define HISI_SPI_ISR 0x24 /* interrupt status register */
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#define HISI_SPI_ICR 0x28 /* interrupt clear register */
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#define HISI_SPI_VERSION 0xe0 /* version register */
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/* Bit fields in HISI_SPI_CR */
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#define CR_LOOP_MASK GENMASK(1, 1)
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#define CR_CPOL_MASK GENMASK(2, 2)
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#define CR_CPHA_MASK GENMASK(3, 3)
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#define CR_DIV_PRE_MASK GENMASK(11, 4)
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#define CR_DIV_POST_MASK GENMASK(19, 12)
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#define CR_BPW_MASK GENMASK(24, 20)
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#define CR_SPD_MODE_MASK GENMASK(25, 25)
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/* Bit fields in HISI_SPI_FIFOC */
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#define FIFOC_TX_MASK GENMASK(5, 3)
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#define FIFOC_RX_MASK GENMASK(11, 9)
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/* Bit fields in HISI_SPI_IMR, 4 bits */
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#define IMR_RXOF BIT(0) /* Receive Overflow */
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#define IMR_RXTO BIT(1) /* Receive Timeout */
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#define IMR_RX BIT(2) /* Receive */
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#define IMR_TX BIT(3) /* Transmit */
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#define IMR_MASK (IMR_RXOF | IMR_RXTO | IMR_RX | IMR_TX)
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/* Bit fields in HISI_SPI_SR, 5 bits */
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#define SR_TXE BIT(0) /* Transmit FIFO empty */
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#define SR_TXNF BIT(1) /* Transmit FIFO not full */
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#define SR_RXNE BIT(2) /* Receive FIFO not empty */
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#define SR_RXF BIT(3) /* Receive FIFO full */
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#define SR_BUSY BIT(4) /* Busy Flag */
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/* Bit fields in HISI_SPI_ISR, 4 bits */
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#define ISR_RXOF BIT(0) /* Receive Overflow */
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#define ISR_RXTO BIT(1) /* Receive Timeout */
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#define ISR_RX BIT(2) /* Receive */
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#define ISR_TX BIT(3) /* Transmit */
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#define ISR_MASK (ISR_RXOF | ISR_RXTO | ISR_RX | ISR_TX)
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/* Bit fields in HISI_SPI_ICR, 2 bits */
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#define ICR_RXOF BIT(0) /* Receive Overflow */
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#define ICR_RXTO BIT(1) /* Receive Timeout */
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#define ICR_MASK (ICR_RXOF | ICR_RXTO)
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#define DIV_POST_MAX 0xFF
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#define DIV_POST_MIN 0x00
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#define DIV_PRE_MAX 0xFE
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#define DIV_PRE_MIN 0x02
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#define CLK_DIV_MAX ((1 + DIV_POST_MAX) * DIV_PRE_MAX)
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#define CLK_DIV_MIN ((1 + DIV_POST_MIN) * DIV_PRE_MIN)
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#define DEFAULT_NUM_CS 1
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#define HISI_SPI_WAIT_TIMEOUT_MS 10UL
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enum hisi_spi_rx_level_trig {
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HISI_SPI_RX_1,
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HISI_SPI_RX_4,
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HISI_SPI_RX_8,
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HISI_SPI_RX_16,
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HISI_SPI_RX_32,
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HISI_SPI_RX_64,
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HISI_SPI_RX_128
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};
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enum hisi_spi_tx_level_trig {
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HISI_SPI_TX_1_OR_LESS,
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HISI_SPI_TX_4_OR_LESS,
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HISI_SPI_TX_8_OR_LESS,
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HISI_SPI_TX_16_OR_LESS,
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HISI_SPI_TX_32_OR_LESS,
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HISI_SPI_TX_64_OR_LESS,
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HISI_SPI_TX_128_OR_LESS
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};
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enum hisi_spi_frame_n_bytes {
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HISI_SPI_N_BYTES_NULL,
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HISI_SPI_N_BYTES_U8,
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HISI_SPI_N_BYTES_U16,
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HISI_SPI_N_BYTES_U32 = 4
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};
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/* Slave spi_dev related */
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struct hisi_chip_data {
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u32 cr;
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u32 speed_hz; /* baud rate */
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u16 clk_div; /* baud rate divider */
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/* clk_div = (1 + div_post) * div_pre */
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u8 div_post; /* value from 0 to 255 */
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u8 div_pre; /* value from 2 to 254 (even only!) */
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};
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struct hisi_spi {
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struct device *dev;
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void __iomem *regs;
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int irq;
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u32 fifo_len; /* depth of the FIFO buffer */
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/* Current message transfer state info */
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const void *tx;
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unsigned int tx_len;
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void *rx;
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unsigned int rx_len;
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u8 n_bytes; /* current is a 1/2/4 bytes op */
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struct dentry *debugfs;
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struct debugfs_regset32 regset;
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};
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#define HISI_SPI_DBGFS_REG(_name, _off) \
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{ \
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.name = _name, \
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.offset = _off, \
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}
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static const struct debugfs_reg32 hisi_spi_regs[] = {
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HISI_SPI_DBGFS_REG("CSCR", HISI_SPI_CSCR),
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HISI_SPI_DBGFS_REG("CR", HISI_SPI_CR),
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HISI_SPI_DBGFS_REG("ENR", HISI_SPI_ENR),
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HISI_SPI_DBGFS_REG("FIFOC", HISI_SPI_FIFOC),
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HISI_SPI_DBGFS_REG("IMR", HISI_SPI_IMR),
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HISI_SPI_DBGFS_REG("DIN", HISI_SPI_DIN),
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HISI_SPI_DBGFS_REG("DOUT", HISI_SPI_DOUT),
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HISI_SPI_DBGFS_REG("SR", HISI_SPI_SR),
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HISI_SPI_DBGFS_REG("RISR", HISI_SPI_RISR),
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HISI_SPI_DBGFS_REG("ISR", HISI_SPI_ISR),
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HISI_SPI_DBGFS_REG("ICR", HISI_SPI_ICR),
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HISI_SPI_DBGFS_REG("VERSION", HISI_SPI_VERSION),
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};
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static int hisi_spi_debugfs_init(struct hisi_spi *hs)
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{
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char name[32];
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struct spi_controller *host;
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host = container_of(hs->dev, struct spi_controller, dev);
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snprintf(name, 32, "hisi_spi%d", host->bus_num);
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hs->debugfs = debugfs_create_dir(name, NULL);
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if (IS_ERR(hs->debugfs))
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return -ENOMEM;
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hs->regset.regs = hisi_spi_regs;
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hs->regset.nregs = ARRAY_SIZE(hisi_spi_regs);
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hs->regset.base = hs->regs;
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debugfs_create_regset32("registers", 0400, hs->debugfs, &hs->regset);
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return 0;
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}
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static u32 hisi_spi_busy(struct hisi_spi *hs)
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{
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return readl(hs->regs + HISI_SPI_SR) & SR_BUSY;
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}
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static u32 hisi_spi_rx_not_empty(struct hisi_spi *hs)
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{
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return readl(hs->regs + HISI_SPI_SR) & SR_RXNE;
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}
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static u32 hisi_spi_tx_not_full(struct hisi_spi *hs)
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{
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return readl(hs->regs + HISI_SPI_SR) & SR_TXNF;
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}
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static void hisi_spi_flush_fifo(struct hisi_spi *hs)
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{
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unsigned long limit = loops_per_jiffy << 1;
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do {
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while (hisi_spi_rx_not_empty(hs))
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readl(hs->regs + HISI_SPI_DOUT);
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} while (hisi_spi_busy(hs) && limit--);
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}
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/* Disable the controller and all interrupts */
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static void hisi_spi_disable(struct hisi_spi *hs)
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{
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writel(0, hs->regs + HISI_SPI_ENR);
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writel(IMR_MASK, hs->regs + HISI_SPI_IMR);
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writel(ICR_MASK, hs->regs + HISI_SPI_ICR);
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}
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static u8 hisi_spi_n_bytes(struct spi_transfer *transfer)
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{
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if (transfer->bits_per_word <= 8)
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return HISI_SPI_N_BYTES_U8;
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else if (transfer->bits_per_word <= 16)
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return HISI_SPI_N_BYTES_U16;
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else
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return HISI_SPI_N_BYTES_U32;
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}
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static void hisi_spi_reader(struct hisi_spi *hs)
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{
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u32 max = min_t(u32, hs->rx_len, hs->fifo_len);
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u32 rxw;
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while (hisi_spi_rx_not_empty(hs) && max--) {
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rxw = readl(hs->regs + HISI_SPI_DOUT);
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/* Check the transfer's original "rx" is not null */
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if (hs->rx) {
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switch (hs->n_bytes) {
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case HISI_SPI_N_BYTES_U8:
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*(u8 *)(hs->rx) = rxw;
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break;
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case HISI_SPI_N_BYTES_U16:
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*(u16 *)(hs->rx) = rxw;
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break;
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case HISI_SPI_N_BYTES_U32:
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*(u32 *)(hs->rx) = rxw;
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break;
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}
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hs->rx += hs->n_bytes;
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}
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--hs->rx_len;
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}
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}
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static void hisi_spi_writer(struct hisi_spi *hs)
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{
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u32 max = min_t(u32, hs->tx_len, hs->fifo_len);
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u32 txw = 0;
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while (hisi_spi_tx_not_full(hs) && max--) {
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/* Check the transfer's original "tx" is not null */
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if (hs->tx) {
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switch (hs->n_bytes) {
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case HISI_SPI_N_BYTES_U8:
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txw = *(u8 *)(hs->tx);
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break;
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case HISI_SPI_N_BYTES_U16:
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txw = *(u16 *)(hs->tx);
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break;
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case HISI_SPI_N_BYTES_U32:
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txw = *(u32 *)(hs->tx);
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break;
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}
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hs->tx += hs->n_bytes;
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}
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writel(txw, hs->regs + HISI_SPI_DIN);
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--hs->tx_len;
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}
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}
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static void __hisi_calc_div_reg(struct hisi_chip_data *chip)
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{
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chip->div_pre = DIV_PRE_MAX;
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while (chip->div_pre >= DIV_PRE_MIN) {
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if (chip->clk_div % chip->div_pre == 0)
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break;
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chip->div_pre -= 2;
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}
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if (chip->div_pre > chip->clk_div)
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chip->div_pre = chip->clk_div;
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chip->div_post = (chip->clk_div / chip->div_pre) - 1;
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}
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static u32 hisi_calc_effective_speed(struct spi_controller *host,
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struct hisi_chip_data *chip, u32 speed_hz)
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{
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u32 effective_speed;
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/* Note clock divider doesn't support odd numbers */
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chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1;
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chip->clk_div &= 0xfffe;
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if (chip->clk_div > CLK_DIV_MAX)
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chip->clk_div = CLK_DIV_MAX;
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effective_speed = host->max_speed_hz / chip->clk_div;
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if (chip->speed_hz != effective_speed) {
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__hisi_calc_div_reg(chip);
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chip->speed_hz = effective_speed;
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}
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return effective_speed;
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}
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static u32 hisi_spi_prepare_cr(struct spi_device *spi)
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{
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u32 cr = FIELD_PREP(CR_SPD_MODE_MASK, 1);
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cr |= FIELD_PREP(CR_CPHA_MASK, (spi->mode & SPI_CPHA) ? 1 : 0);
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cr |= FIELD_PREP(CR_CPOL_MASK, (spi->mode & SPI_CPOL) ? 1 : 0);
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cr |= FIELD_PREP(CR_LOOP_MASK, (spi->mode & SPI_LOOP) ? 1 : 0);
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return cr;
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}
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static void hisi_spi_hw_init(struct hisi_spi *hs)
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{
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hisi_spi_disable(hs);
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/* FIFO default config */
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writel(FIELD_PREP(FIFOC_TX_MASK, HISI_SPI_TX_64_OR_LESS) |
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FIELD_PREP(FIFOC_RX_MASK, HISI_SPI_RX_16),
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hs->regs + HISI_SPI_FIFOC);
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hs->fifo_len = 256;
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}
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static irqreturn_t hisi_spi_irq(int irq, void *dev_id)
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{
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struct spi_controller *host = dev_id;
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struct hisi_spi *hs = spi_controller_get_devdata(host);
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u32 irq_status = readl(hs->regs + HISI_SPI_ISR) & ISR_MASK;
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if (!irq_status)
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return IRQ_NONE;
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if (!host->cur_msg)
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return IRQ_HANDLED;
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/* Error handling */
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if (irq_status & ISR_RXOF) {
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dev_err(hs->dev, "interrupt_transfer: fifo overflow\n");
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host->cur_msg->status = -EIO;
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goto finalize_transfer;
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}
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/*
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* Read data from the Rx FIFO every time. If there is
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* nothing left to receive, finalize the transfer.
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*/
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hisi_spi_reader(hs);
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if (!hs->rx_len)
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goto finalize_transfer;
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/* Send data out when Tx FIFO IRQ triggered */
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if (irq_status & ISR_TX)
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hisi_spi_writer(hs);
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return IRQ_HANDLED;
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finalize_transfer:
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hisi_spi_disable(hs);
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spi_finalize_current_transfer(host);
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return IRQ_HANDLED;
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}
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static int hisi_spi_transfer_one(struct spi_controller *host,
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struct spi_device *spi, struct spi_transfer *transfer)
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{
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struct hisi_spi *hs = spi_controller_get_devdata(host);
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struct hisi_chip_data *chip = spi_get_ctldata(spi);
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u32 cr = chip->cr;
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/* Update per transfer options for speed and bpw */
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transfer->effective_speed_hz =
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hisi_calc_effective_speed(host, chip, transfer->speed_hz);
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cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre);
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cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post);
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cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1);
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writel(cr, hs->regs + HISI_SPI_CR);
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hisi_spi_flush_fifo(hs);
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hs->n_bytes = hisi_spi_n_bytes(transfer);
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hs->tx = transfer->tx_buf;
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hs->tx_len = transfer->len / hs->n_bytes;
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hs->rx = transfer->rx_buf;
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hs->rx_len = hs->tx_len;
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/*
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* Ensure that the transfer data above has been updated
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* before the interrupt to start.
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*/
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smp_mb();
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/* Enable all interrupts and the controller */
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writel(~(u32)IMR_MASK, hs->regs + HISI_SPI_IMR);
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writel(1, hs->regs + HISI_SPI_ENR);
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return 1;
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}
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static void hisi_spi_handle_err(struct spi_controller *host,
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struct spi_message *msg)
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{
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struct hisi_spi *hs = spi_controller_get_devdata(host);
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hisi_spi_disable(hs);
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/*
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* Wait for interrupt handler that is
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* already in timeout to complete.
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*/
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msleep(HISI_SPI_WAIT_TIMEOUT_MS);
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}
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static int hisi_spi_setup(struct spi_device *spi)
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{
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struct hisi_chip_data *chip;
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/* Only alloc on first setup */
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chip = spi_get_ctldata(spi);
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if (!chip) {
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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spi_set_ctldata(spi, chip);
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}
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chip->cr = hisi_spi_prepare_cr(spi);
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return 0;
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}
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static void hisi_spi_cleanup(struct spi_device *spi)
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{
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struct hisi_chip_data *chip = spi_get_ctldata(spi);
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kfree(chip);
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spi_set_ctldata(spi, NULL);
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}
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static int hisi_spi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spi_controller *host;
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struct hisi_spi *hs;
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int ret, irq;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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host = devm_spi_alloc_host(dev, sizeof(*hs));
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if (!host)
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return -ENOMEM;
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platform_set_drvdata(pdev, host);
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hs = spi_controller_get_devdata(host);
|
|
hs->dev = dev;
|
|
hs->irq = irq;
|
|
|
|
hs->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(hs->regs))
|
|
return PTR_ERR(hs->regs);
|
|
|
|
/* Specify maximum SPI clocking speed (host only) by firmware */
|
|
ret = device_property_read_u32(dev, "spi-max-frequency",
|
|
&host->max_speed_hz);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get max SPI clocking speed, ret=%d\n",
|
|
ret);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = device_property_read_u16(dev, "num-cs",
|
|
&host->num_chipselect);
|
|
if (ret)
|
|
host->num_chipselect = DEFAULT_NUM_CS;
|
|
|
|
host->use_gpio_descriptors = true;
|
|
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
|
|
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
|
host->bus_num = pdev->id;
|
|
host->setup = hisi_spi_setup;
|
|
host->cleanup = hisi_spi_cleanup;
|
|
host->transfer_one = hisi_spi_transfer_one;
|
|
host->handle_err = hisi_spi_handle_err;
|
|
host->dev.fwnode = dev->fwnode;
|
|
|
|
hisi_spi_hw_init(hs);
|
|
|
|
ret = devm_request_irq(dev, hs->irq, hisi_spi_irq, 0, dev_name(dev),
|
|
host);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get IRQ=%d, ret=%d\n", hs->irq, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = spi_register_controller(host);
|
|
if (ret) {
|
|
dev_err(dev, "failed to register spi host, ret=%d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
if (hisi_spi_debugfs_init(hs))
|
|
dev_info(dev, "failed to create debugfs dir\n");
|
|
|
|
dev_info(dev, "hw version:0x%x max-freq:%u kHz\n",
|
|
readl(hs->regs + HISI_SPI_VERSION),
|
|
host->max_speed_hz / 1000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hisi_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_controller *host = platform_get_drvdata(pdev);
|
|
struct hisi_spi *hs = spi_controller_get_devdata(host);
|
|
|
|
debugfs_remove_recursive(hs->debugfs);
|
|
spi_unregister_controller(host);
|
|
}
|
|
|
|
static const struct acpi_device_id hisi_spi_acpi_match[] = {
|
|
{"HISI03E1", 0},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, hisi_spi_acpi_match);
|
|
|
|
static struct platform_driver hisi_spi_driver = {
|
|
.probe = hisi_spi_probe,
|
|
.remove_new = hisi_spi_remove,
|
|
.driver = {
|
|
.name = "hisi-kunpeng-spi",
|
|
.acpi_match_table = hisi_spi_acpi_match,
|
|
},
|
|
};
|
|
module_platform_driver(hisi_spi_driver);
|
|
|
|
MODULE_AUTHOR("Jay Fang <f.fangjian@huawei.com>");
|
|
MODULE_DESCRIPTION("HiSilicon SPI Controller Driver for Kunpeng SoCs");
|
|
MODULE_LICENSE("GPL v2");
|