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Suspend to RAM on Odroid XU3/XU4/HC1 family (Exynos5422) causes imprecise abort: PM: Syncing filesystems ... done. Freezing user space processes ... (elapsed 0.003 seconds) done. OOM killer disabled. Freezing remaining freezable tasks ... (elapsed 0.003 seconds) done. wake enabled for irq 139 Disabling non-boot CPUs ... IRQ51 no longer affine to CPU1 IRQ52 no longer affine to CPU2 IRQ53 no longer affine to CPU3 IRQ54 no longer affine to CPU4 IRQ55 no longer affine to CPU5 IRQ56 no longer affine to CPU6 cpu cpu4: Dropping the link to regulator.40 IRQ57 no longer affine to CPU7 Unhandled fault: external abort on non-linefetch (0x1008) at 0xf081a028 Internal error: : 1008 [#1] PREEMPT SMP ARM with last call trace in exynos_suspend_enter(). The abort is caused by writing to register in secure part of sysram. Boards booted under secure firmware (e.g. Hardkernel Odroid boards) should access non-secure sysram. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
69 lines
3.1 KiB
Plaintext
69 lines
3.1 KiB
Plaintext
Interface between kernel and boot loaders on Exynos boards
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==========================================================
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Author: Krzysztof Kozlowski
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Date : 6 June 2015
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The document tries to describe currently used interface between Linux kernel
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and boot loaders on Samsung Exynos based boards. This is not a definition
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of interface but rather a description of existing state, a reference
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for information purpose only.
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In the document "boot loader" means any of following: U-boot, proprietary
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SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before
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executing kernel.
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1. Non-Secure mode
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Address: sysram_ns_base_addr
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Offset Value Purpose
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=============================================================================
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0x08 exynos_cpu_resume_ns, mcpm_entry_point System suspend
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0x0c 0x00000bad (Magic cookie) System suspend
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0x1c exynos4_secondary_startup Secondary CPU boot
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0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
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0x20 0xfcba0d10 (Magic cookie) AFTR
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0x24 exynos_cpu_resume_ns AFTR
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0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR
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0x28 0x0 or last value during resume (Exynos542x) System suspend
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2. Secure mode
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Address: sysram_base_addr
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Offset Value Purpose
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=============================================================================
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0x00 exynos4_secondary_startup Secondary CPU boot
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0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
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4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
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0x20 exynos_cpu_resume (Exynos4210 r1.0) AFTR
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0x24 0xfcba0d10 (Magic cookie, Exynos4210 r1.0) AFTR
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Address: pmu_base_addr
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Offset Value Purpose
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=============================================================================
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0x0800 exynos_cpu_resume AFTR, suspend
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0x0800 mcpm_entry_point (Exynos542x with MCPM) AFTR, suspend
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0x0804 0xfcba0d10 (Magic cookie) AFTR
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0x0804 0x00000bad (Magic cookie) System suspend
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0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot
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0x0818 0xfcba0d10 (Magic cookie, Exynos4210 r1.1) AFTR
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0x081C exynos_cpu_resume (Exynos4210 r1.1) AFTR
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3. Other (regardless of secure/non-secure mode)
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Address: pmu_base_addr
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Offset Value Purpose
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=============================================================================
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0x0908 Non-zero Secondary CPU boot up indicator
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on Exynos3250 and Exynos542x
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4. Glossary
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AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
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modules are power gated, except the TOP modules
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MCPM - Multi-Cluster Power Management
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