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20413113ff
Add a field with the tx/rx register address to the DMA parameters structure, and set it to the correct address during device initialization. This address used to be hardcoded in the DMA controller driver, it now needs to be explicitly figured out by the device driver. Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
711 lines
19 KiB
C
711 lines
19 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2012
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*
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* Author: Ola Lilja <ola.o.lilja@stericsson.com>,
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* Roger Nilsson <roger.xr.nilsson@stericsson.com>,
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* Sandeep Kaushik <sandeep.kaushik@st.com>
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* for ST-Ericsson.
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*
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* License terms:
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/platform_data/asoc-ux500-msp.h>
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#include <sound/soc.h>
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#include "ux500_msp_i2s.h"
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/* Protocol desciptors */
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static const struct msp_protdesc prot_descs[] = {
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{ /* I2S */
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MSP_SINGLE_PHASE,
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MSP_SINGLE_PHASE,
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MSP_PHASE2_START_MODE_IMEDIATE,
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MSP_PHASE2_START_MODE_IMEDIATE,
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MSP_BTF_MS_BIT_FIRST,
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MSP_BTF_MS_BIT_FIRST,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_ELEM_LEN_32,
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MSP_ELEM_LEN_32,
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MSP_ELEM_LEN_32,
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MSP_ELEM_LEN_32,
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MSP_DELAY_1,
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MSP_DELAY_1,
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MSP_RISING_EDGE,
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MSP_FALLING_EDGE,
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MSP_FSYNC_POL_ACT_LO,
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MSP_FSYNC_POL_ACT_LO,
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MSP_SWAP_NONE,
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MSP_SWAP_NONE,
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MSP_COMPRESS_MODE_LINEAR,
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MSP_EXPAND_MODE_LINEAR,
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MSP_FSYNC_IGNORE,
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31,
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15,
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32,
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}, { /* PCM */
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MSP_DUAL_PHASE,
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MSP_DUAL_PHASE,
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MSP_PHASE2_START_MODE_FSYNC,
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MSP_PHASE2_START_MODE_FSYNC,
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MSP_BTF_MS_BIT_FIRST,
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MSP_BTF_MS_BIT_FIRST,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_ELEM_LEN_16,
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MSP_ELEM_LEN_16,
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MSP_ELEM_LEN_16,
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MSP_ELEM_LEN_16,
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MSP_DELAY_0,
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MSP_DELAY_0,
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MSP_RISING_EDGE,
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MSP_FALLING_EDGE,
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MSP_FSYNC_POL_ACT_HI,
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MSP_FSYNC_POL_ACT_HI,
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MSP_SWAP_NONE,
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MSP_SWAP_NONE,
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MSP_COMPRESS_MODE_LINEAR,
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MSP_EXPAND_MODE_LINEAR,
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MSP_FSYNC_IGNORE,
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255,
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0,
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256,
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}, { /* Companded PCM */
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MSP_SINGLE_PHASE,
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MSP_SINGLE_PHASE,
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MSP_PHASE2_START_MODE_FSYNC,
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MSP_PHASE2_START_MODE_FSYNC,
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MSP_BTF_MS_BIT_FIRST,
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MSP_BTF_MS_BIT_FIRST,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_FRAME_LEN_1,
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MSP_ELEM_LEN_8,
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MSP_ELEM_LEN_8,
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MSP_ELEM_LEN_8,
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MSP_ELEM_LEN_8,
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MSP_DELAY_0,
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MSP_DELAY_0,
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MSP_RISING_EDGE,
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MSP_RISING_EDGE,
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MSP_FSYNC_POL_ACT_HI,
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MSP_FSYNC_POL_ACT_HI,
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MSP_SWAP_NONE,
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MSP_SWAP_NONE,
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MSP_COMPRESS_MODE_LINEAR,
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MSP_EXPAND_MODE_LINEAR,
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MSP_FSYNC_IGNORE,
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255,
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0,
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256,
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},
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};
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static void set_prot_desc_tx(struct ux500_msp *msp,
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struct msp_protdesc *protdesc,
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enum msp_data_size data_size)
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{
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u32 temp_reg = 0;
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temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode);
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temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode);
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temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1);
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temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2);
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if (msp->def_elem_len) {
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temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1);
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temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2);
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} else {
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temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
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temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
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}
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temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay);
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temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order);
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temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol);
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temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap);
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temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode);
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temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
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writel(temp_reg, msp->registers + MSP_TCF);
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}
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static void set_prot_desc_rx(struct ux500_msp *msp,
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struct msp_protdesc *protdesc,
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enum msp_data_size data_size)
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{
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u32 temp_reg = 0;
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temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode);
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temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode);
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temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1);
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temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2);
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if (msp->def_elem_len) {
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temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1);
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temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2);
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} else {
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temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
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temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
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}
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temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay);
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temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order);
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temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol);
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temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap);
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temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode);
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temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
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writel(temp_reg, msp->registers + MSP_RCF);
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}
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static int configure_protocol(struct ux500_msp *msp,
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struct ux500_msp_config *config)
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{
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struct msp_protdesc *protdesc;
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enum msp_data_size data_size;
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u32 temp_reg = 0;
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data_size = config->data_size;
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msp->def_elem_len = config->def_elem_len;
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if (config->default_protdesc == 1) {
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if (config->protocol >= MSP_INVALID_PROTOCOL) {
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dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n",
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__func__);
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return -EINVAL;
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}
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protdesc =
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(struct msp_protdesc *)&prot_descs[config->protocol];
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} else {
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protdesc = (struct msp_protdesc *)&config->protdesc;
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}
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if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) {
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dev_err(msp->dev,
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"%s: ERROR: Invalid data-size requested (data_size = %d)!\n",
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__func__, data_size);
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return -EINVAL;
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}
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if (config->direction & MSP_DIR_TX)
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set_prot_desc_tx(msp, protdesc, data_size);
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if (config->direction & MSP_DIR_RX)
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set_prot_desc_rx(msp, protdesc, data_size);
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/* The code below should not be separated. */
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temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;
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temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol);
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writel(temp_reg, msp->registers + MSP_GCR);
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temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;
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temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol);
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writel(temp_reg, msp->registers + MSP_GCR);
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return 0;
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}
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static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config)
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{
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u32 reg_val_GCR;
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u32 frame_per = 0;
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u32 sck_div = 0;
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u32 frame_width = 0;
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u32 temp_reg = 0;
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struct msp_protdesc *protdesc = NULL;
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
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if (config->default_protdesc)
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protdesc =
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(struct msp_protdesc *)&prot_descs[config->protocol];
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else
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protdesc = (struct msp_protdesc *)&config->protdesc;
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switch (config->protocol) {
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case MSP_PCM_PROTOCOL:
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case MSP_PCM_COMPAND_PROTOCOL:
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frame_width = protdesc->frame_width;
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sck_div = config->f_inputclk / (config->frame_freq *
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(protdesc->clocks_per_frame));
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frame_per = protdesc->frame_period;
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break;
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case MSP_I2S_PROTOCOL:
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frame_width = protdesc->frame_width;
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sck_div = config->f_inputclk / (config->frame_freq *
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(protdesc->clocks_per_frame));
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frame_per = protdesc->frame_period;
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break;
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default:
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dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n",
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__func__,
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config->protocol);
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return -EINVAL;
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}
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temp_reg = (sck_div - 1) & SCK_DIV_MASK;
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temp_reg |= FRAME_WIDTH_BITS(frame_width);
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temp_reg |= FRAME_PERIOD_BITS(frame_per);
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writel(temp_reg, msp->registers + MSP_SRG);
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msp->f_bitclk = (config->f_inputclk)/(sck_div + 1);
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/* Enable bit-clock */
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udelay(100);
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
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udelay(100);
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return 0;
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}
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static int configure_multichannel(struct ux500_msp *msp,
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struct ux500_msp_config *config)
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{
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struct msp_protdesc *protdesc;
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struct msp_multichannel_config *mcfg;
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u32 reg_val_MCR;
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if (config->default_protdesc == 1) {
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if (config->protocol >= MSP_INVALID_PROTOCOL) {
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dev_err(msp->dev,
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"%s: ERROR: Invalid protocol (%d)!\n",
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__func__, config->protocol);
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return -EINVAL;
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}
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protdesc = (struct msp_protdesc *)
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&prot_descs[config->protocol];
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} else {
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protdesc = (struct msp_protdesc *)&config->protdesc;
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}
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mcfg = &config->multichannel_config;
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if (mcfg->tx_multichannel_enable) {
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if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) {
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reg_val_MCR = readl(msp->registers + MSP_MCR);
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writel(reg_val_MCR | (mcfg->tx_multichannel_enable ?
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1 << TMCEN_BIT : 0),
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msp->registers + MSP_MCR);
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writel(mcfg->tx_channel_0_enable,
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msp->registers + MSP_TCE0);
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writel(mcfg->tx_channel_1_enable,
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msp->registers + MSP_TCE1);
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writel(mcfg->tx_channel_2_enable,
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msp->registers + MSP_TCE2);
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writel(mcfg->tx_channel_3_enable,
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msp->registers + MSP_TCE3);
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} else {
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dev_err(msp->dev,
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"%s: ERROR: Only single-phase supported (TX-mode: %d)!\n",
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__func__, protdesc->tx_phase_mode);
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return -EINVAL;
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}
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}
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if (mcfg->rx_multichannel_enable) {
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if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) {
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reg_val_MCR = readl(msp->registers + MSP_MCR);
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writel(reg_val_MCR | (mcfg->rx_multichannel_enable ?
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1 << RMCEN_BIT : 0),
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msp->registers + MSP_MCR);
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writel(mcfg->rx_channel_0_enable,
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msp->registers + MSP_RCE0);
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writel(mcfg->rx_channel_1_enable,
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msp->registers + MSP_RCE1);
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writel(mcfg->rx_channel_2_enable,
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msp->registers + MSP_RCE2);
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writel(mcfg->rx_channel_3_enable,
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msp->registers + MSP_RCE3);
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} else {
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dev_err(msp->dev,
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"%s: ERROR: Only single-phase supported (RX-mode: %d)!\n",
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__func__, protdesc->rx_phase_mode);
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return -EINVAL;
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}
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if (mcfg->rx_comparison_enable_mode) {
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reg_val_MCR = readl(msp->registers + MSP_MCR);
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writel(reg_val_MCR |
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(mcfg->rx_comparison_enable_mode << RCMPM_BIT),
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msp->registers + MSP_MCR);
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writel(mcfg->comparison_mask,
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msp->registers + MSP_RCM);
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writel(mcfg->comparison_value,
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msp->registers + MSP_RCV);
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}
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}
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return 0;
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}
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static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
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{
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int status = 0;
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u32 reg_val_DMACR, reg_val_GCR;
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/* Configure msp with protocol dependent settings */
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configure_protocol(msp, config);
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setup_bitclk(msp, config);
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if (config->multichannel_configured == 1) {
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status = configure_multichannel(msp, config);
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if (status)
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dev_warn(msp->dev,
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"%s: WARN: configure_multichannel failed (%d)!\n",
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__func__, status);
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}
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/* Make sure the correct DMA-directions are configured */
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if ((config->direction & MSP_DIR_RX) &&
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!msp->capture_dma_data.dma_cfg) {
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dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!",
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__func__);
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return -EINVAL;
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}
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if ((config->direction == MSP_DIR_TX) &&
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!msp->playback_dma_data.dma_cfg) {
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dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!",
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__func__);
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return -EINVAL;
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}
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reg_val_DMACR = readl(msp->registers + MSP_DMACR);
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if (config->direction & MSP_DIR_RX)
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reg_val_DMACR |= RX_DMA_ENABLE;
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if (config->direction & MSP_DIR_TX)
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reg_val_DMACR |= TX_DMA_ENABLE;
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writel(reg_val_DMACR, msp->registers + MSP_DMACR);
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writel(config->iodelay, msp->registers + MSP_IODLY);
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/* Enable frame generation logic */
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
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return status;
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}
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static void flush_fifo_rx(struct ux500_msp *msp)
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{
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u32 reg_val_DR, reg_val_GCR, reg_val_FLR;
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u32 limit = 32;
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
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reg_val_DR = readl(msp->registers + MSP_DR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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}
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writel(reg_val_GCR, msp->registers + MSP_GCR);
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}
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static void flush_fifo_tx(struct ux500_msp *msp)
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{
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u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR;
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u32 limit = 32;
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reg_val_GCR = readl(msp->registers + MSP_GCR);
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writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
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writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
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reg_val_FLR = readl(msp->registers + MSP_FLR);
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while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
|
|
reg_val_TSTDR = readl(msp->registers + MSP_TSTDR);
|
|
reg_val_FLR = readl(msp->registers + MSP_FLR);
|
|
}
|
|
writel(0x0, msp->registers + MSP_ITCR);
|
|
writel(reg_val_GCR, msp->registers + MSP_GCR);
|
|
}
|
|
|
|
int ux500_msp_i2s_open(struct ux500_msp *msp,
|
|
struct ux500_msp_config *config)
|
|
{
|
|
u32 old_reg, new_reg, mask;
|
|
int res;
|
|
unsigned int tx_sel, rx_sel, tx_busy, rx_busy;
|
|
|
|
if (in_interrupt()) {
|
|
dev_err(msp->dev,
|
|
"%s: ERROR: Open called in interrupt context!\n",
|
|
__func__);
|
|
return -1;
|
|
}
|
|
|
|
tx_sel = (config->direction & MSP_DIR_TX) > 0;
|
|
rx_sel = (config->direction & MSP_DIR_RX) > 0;
|
|
if (!tx_sel && !rx_sel) {
|
|
dev_err(msp->dev, "%s: Error: No direction selected!\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0;
|
|
rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0;
|
|
if (tx_busy && tx_sel) {
|
|
dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__);
|
|
return -EBUSY;
|
|
}
|
|
if (rx_busy && rx_sel) {
|
|
dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__);
|
|
return -EBUSY;
|
|
}
|
|
|
|
msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
|
|
|
|
/* First do the global config register */
|
|
mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK |
|
|
TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK |
|
|
RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK |
|
|
LOOPBACK_MASK | TX_EXTRA_DELAY_MASK;
|
|
|
|
new_reg = (config->tx_clk_sel | config->rx_clk_sel |
|
|
config->rx_fsync_pol | config->tx_fsync_pol |
|
|
config->rx_fsync_sel | config->tx_fsync_sel |
|
|
config->rx_fifo_config | config->tx_fifo_config |
|
|
config->srg_clk_sel | config->loopback_enable |
|
|
config->tx_data_enable);
|
|
|
|
old_reg = readl(msp->registers + MSP_GCR);
|
|
old_reg &= ~mask;
|
|
new_reg |= old_reg;
|
|
writel(new_reg, msp->registers + MSP_GCR);
|
|
|
|
res = enable_msp(msp, config);
|
|
if (res < 0) {
|
|
dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
|
|
__func__, res);
|
|
return -EBUSY;
|
|
}
|
|
if (config->loopback_enable & 0x80)
|
|
msp->loopback_enable = 1;
|
|
|
|
/* Flush FIFOs */
|
|
flush_fifo_tx(msp);
|
|
flush_fifo_rx(msp);
|
|
|
|
msp->msp_state = MSP_STATE_CONFIGURED;
|
|
return 0;
|
|
}
|
|
|
|
static void disable_msp_rx(struct ux500_msp *msp)
|
|
{
|
|
u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
|
|
|
|
reg_val_GCR = readl(msp->registers + MSP_GCR);
|
|
writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
|
|
reg_val_DMACR = readl(msp->registers + MSP_DMACR);
|
|
writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
|
|
reg_val_IMSC = readl(msp->registers + MSP_IMSC);
|
|
writel(reg_val_IMSC &
|
|
~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT),
|
|
msp->registers + MSP_IMSC);
|
|
|
|
msp->dir_busy &= ~MSP_DIR_RX;
|
|
}
|
|
|
|
static void disable_msp_tx(struct ux500_msp *msp)
|
|
{
|
|
u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
|
|
|
|
reg_val_GCR = readl(msp->registers + MSP_GCR);
|
|
writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
|
|
reg_val_DMACR = readl(msp->registers + MSP_DMACR);
|
|
writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
|
|
reg_val_IMSC = readl(msp->registers + MSP_IMSC);
|
|
writel(reg_val_IMSC &
|
|
~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT),
|
|
msp->registers + MSP_IMSC);
|
|
|
|
msp->dir_busy &= ~MSP_DIR_TX;
|
|
}
|
|
|
|
static int disable_msp(struct ux500_msp *msp, unsigned int dir)
|
|
{
|
|
u32 reg_val_GCR;
|
|
int status = 0;
|
|
unsigned int disable_tx, disable_rx;
|
|
|
|
reg_val_GCR = readl(msp->registers + MSP_GCR);
|
|
disable_tx = dir & MSP_DIR_TX;
|
|
disable_rx = dir & MSP_DIR_TX;
|
|
if (disable_tx && disable_rx) {
|
|
reg_val_GCR = readl(msp->registers + MSP_GCR);
|
|
writel(reg_val_GCR | LOOPBACK_MASK,
|
|
msp->registers + MSP_GCR);
|
|
|
|
/* Flush TX-FIFO */
|
|
flush_fifo_tx(msp);
|
|
|
|
/* Disable TX-channel */
|
|
writel((readl(msp->registers + MSP_GCR) &
|
|
(~TX_ENABLE)), msp->registers + MSP_GCR);
|
|
|
|
/* Flush RX-FIFO */
|
|
flush_fifo_rx(msp);
|
|
|
|
/* Disable Loopback and Receive channel */
|
|
writel((readl(msp->registers + MSP_GCR) &
|
|
(~(RX_ENABLE | LOOPBACK_MASK))),
|
|
msp->registers + MSP_GCR);
|
|
|
|
disable_msp_tx(msp);
|
|
disable_msp_rx(msp);
|
|
} else if (disable_tx)
|
|
disable_msp_tx(msp);
|
|
else if (disable_rx)
|
|
disable_msp_rx(msp);
|
|
|
|
return status;
|
|
}
|
|
|
|
int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
|
|
{
|
|
u32 reg_val_GCR, enable_bit;
|
|
|
|
if (msp->msp_state == MSP_STATE_IDLE) {
|
|
dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
if (direction == SNDRV_PCM_STREAM_PLAYBACK)
|
|
enable_bit = TX_ENABLE;
|
|
else
|
|
enable_bit = RX_ENABLE;
|
|
reg_val_GCR = readl(msp->registers + MSP_GCR);
|
|
writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
if (direction == SNDRV_PCM_STREAM_PLAYBACK)
|
|
disable_msp_tx(msp);
|
|
else
|
|
disable_msp_rx(msp);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
|
|
{
|
|
int status = 0;
|
|
|
|
dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
|
|
|
|
status = disable_msp(msp, dir);
|
|
if (msp->dir_busy == 0) {
|
|
/* disable sample rate and frame generators */
|
|
msp->msp_state = MSP_STATE_IDLE;
|
|
writel((readl(msp->registers + MSP_GCR) &
|
|
(~(FRAME_GEN_ENABLE | SRG_ENABLE))),
|
|
msp->registers + MSP_GCR);
|
|
|
|
writel(0, msp->registers + MSP_GCR);
|
|
writel(0, msp->registers + MSP_TCF);
|
|
writel(0, msp->registers + MSP_RCF);
|
|
writel(0, msp->registers + MSP_DMACR);
|
|
writel(0, msp->registers + MSP_SRG);
|
|
writel(0, msp->registers + MSP_MCR);
|
|
writel(0, msp->registers + MSP_RCM);
|
|
writel(0, msp->registers + MSP_RCV);
|
|
writel(0, msp->registers + MSP_TCE0);
|
|
writel(0, msp->registers + MSP_TCE1);
|
|
writel(0, msp->registers + MSP_TCE2);
|
|
writel(0, msp->registers + MSP_TCE3);
|
|
writel(0, msp->registers + MSP_RCE0);
|
|
writel(0, msp->registers + MSP_RCE1);
|
|
writel(0, msp->registers + MSP_RCE2);
|
|
writel(0, msp->registers + MSP_RCE3);
|
|
}
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
int ux500_msp_i2s_init_msp(struct platform_device *pdev,
|
|
struct ux500_msp **msp_p,
|
|
struct msp_i2s_platform_data *platform_data)
|
|
{
|
|
struct resource *res = NULL;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct ux500_msp *msp;
|
|
|
|
*msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
|
|
msp = *msp_p;
|
|
if (!msp)
|
|
return -ENOMEM;
|
|
|
|
if (np) {
|
|
if (!platform_data) {
|
|
platform_data = devm_kzalloc(&pdev->dev,
|
|
sizeof(struct msp_i2s_platform_data), GFP_KERNEL);
|
|
if (!platform_data)
|
|
return -ENOMEM;
|
|
}
|
|
} else
|
|
if (!platform_data)
|
|
return -EINVAL;
|
|
|
|
dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
|
|
pdev->name, platform_data->id);
|
|
|
|
msp->id = platform_data->id;
|
|
msp->dev = &pdev->dev;
|
|
msp->playback_dma_data.dma_cfg = platform_data->msp_i2s_dma_tx;
|
|
msp->capture_dma_data.dma_cfg = platform_data->msp_i2s_dma_rx;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (res == NULL) {
|
|
dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n",
|
|
__func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
msp->playback_dma_data.tx_rx_addr = res->start + MSP_DR;
|
|
msp->capture_dma_data.tx_rx_addr = res->start + MSP_DR;
|
|
|
|
msp->registers = devm_ioremap(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
if (msp->registers == NULL) {
|
|
dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
msp->msp_state = MSP_STATE_IDLE;
|
|
msp->loopback_enable = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
|
|
struct ux500_msp *msp)
|
|
{
|
|
dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id);
|
|
}
|
|
|
|
MODULE_LICENSE("GPL v2");
|