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00a9730e10
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
220 lines
4.4 KiB
C
220 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/setup.h>
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#define CSKY_TLB_SIZE CONFIG_CPU_TLB_SIZE
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void flush_tlb_all(void)
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{
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tlb_invalid_all();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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int cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0)
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drop_mmu_context(mm, cpu);
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tlb_invalid_all();
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}
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#define restore_asid_inv_utlb(oldpid, newpid) \
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do { \
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if ((oldpid & ASID_MASK) == newpid) \
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write_mmu_entryhi(oldpid + 1); \
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write_mmu_entryhi(oldpid); \
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} while (0)
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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int cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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unsigned long size, flags;
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int newpid = cpu_asid(cpu, mm);
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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if (size <= CSKY_TLB_SIZE/2) {
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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#ifdef CONFIG_CPU_HAS_TLBI
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while (start < end) {
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asm volatile("tlbi.vaas %0"
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::"r"(start | newpid));
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start += (PAGE_SIZE << 1);
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}
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sync_is();
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#else
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{
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int oldpid = read_mmu_entryhi();
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while (start < end) {
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int idx;
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write_mmu_entryhi(start | newpid);
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start += (PAGE_SIZE << 1);
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tlb_probe();
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idx = read_mmu_index();
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if (idx >= 0)
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tlb_invalid_indexed();
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}
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restore_asid_inv_utlb(oldpid, newpid);
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}
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#endif
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} else {
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drop_mmu_context(mm, cpu);
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}
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local_irq_restore(flags);
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}
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long size, flags;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size <= CSKY_TLB_SIZE) {
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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#ifdef CONFIG_CPU_HAS_TLBI
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while (start < end) {
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asm volatile("tlbi.vaas %0"::"r"(start));
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start += (PAGE_SIZE << 1);
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}
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sync_is();
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#else
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{
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int oldpid = read_mmu_entryhi();
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while (start < end) {
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int idx;
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write_mmu_entryhi(start);
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start += (PAGE_SIZE << 1);
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tlb_probe();
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idx = read_mmu_index();
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if (idx >= 0)
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tlb_invalid_indexed();
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}
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restore_asid_inv_utlb(oldpid, 0);
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}
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#endif
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} else {
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flush_tlb_all();
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}
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local_irq_restore(flags);
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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int cpu = smp_processor_id();
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int newpid = cpu_asid(cpu, vma->vm_mm);
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if (!vma || cpu_context(cpu, vma->vm_mm) != 0) {
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page &= (PAGE_MASK << 1);
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#ifdef CONFIG_CPU_HAS_TLBI
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asm volatile("tlbi.vaas %0"::"r"(page | newpid));
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sync_is();
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#else
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{
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int oldpid, idx;
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unsigned long flags;
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local_irq_save(flags);
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oldpid = read_mmu_entryhi();
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write_mmu_entryhi(page | newpid);
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tlb_probe();
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idx = read_mmu_index();
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if (idx >= 0)
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tlb_invalid_indexed();
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restore_asid_inv_utlb(oldpid, newpid);
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local_irq_restore(flags);
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}
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#endif
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}
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}
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/*
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* Remove one kernel space TLB entry. This entry is assumed to be marked
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* global so we don't do the ASID thing.
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*/
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void flush_tlb_one(unsigned long page)
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{
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int oldpid;
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oldpid = read_mmu_entryhi();
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page &= (PAGE_MASK << 1);
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#ifdef CONFIG_CPU_HAS_TLBI
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page = page | (oldpid & 0xfff);
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asm volatile("tlbi.vaas %0"::"r"(page));
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sync_is();
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#else
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{
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int idx;
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unsigned long flags;
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page = page | (oldpid & 0xff);
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local_irq_save(flags);
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write_mmu_entryhi(page);
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tlb_probe();
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idx = read_mmu_index();
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if (idx >= 0)
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tlb_invalid_indexed();
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restore_asid_inv_utlb(oldpid, oldpid);
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local_irq_restore(flags);
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}
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#endif
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}
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EXPORT_SYMBOL(flush_tlb_one);
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/* show current 32 jtlbs */
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void show_jtlb_table(void)
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{
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unsigned long flags;
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int entryhi, entrylo0, entrylo1;
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int entry;
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int oldpid;
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local_irq_save(flags);
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entry = 0;
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pr_info("\n\n\n");
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oldpid = read_mmu_entryhi();
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while (entry < CSKY_TLB_SIZE) {
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write_mmu_index(entry);
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tlb_read();
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entryhi = read_mmu_entryhi();
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entrylo0 = read_mmu_entrylo0();
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entrylo0 = entrylo0;
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entrylo1 = read_mmu_entrylo1();
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entrylo1 = entrylo1;
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pr_info("jtlb[%d]: entryhi - 0x%x; entrylo0 - 0x%x;"
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" entrylo1 - 0x%x\n",
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entry, entryhi, entrylo0, entrylo1);
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entry++;
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}
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write_mmu_entryhi(oldpid);
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local_irq_restore(flags);
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}
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