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Scalable MCA (SMCA) is a new feature in AMD Fam17h processors which indicates presence of MCA extensions. MCA extensions expands existing register space for the MCE banks and also introduces a new MSR range to accommodate new banks. Add the detection bit. Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> [ Reformat mce_vendor_flags definitions and save indentation levels. Improve comments. ] Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Ashok Raj <ashok.raj@intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1446207099-24948-2-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
291 lines
9.0 KiB
C
291 lines
9.0 KiB
C
#ifndef _ASM_X86_MCE_H
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#define _ASM_X86_MCE_H
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#include <uapi/asm/mce.h>
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/*
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* Machine Check support for x86
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*/
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/* MCG_CAP register defines */
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
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#define MCG_EXT_CNT_SHIFT 16
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
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#define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */
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#define MCG_LMCE_P (1ULL<<27) /* Local machine check supported */
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/* MCG_STATUS register defines */
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#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
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#define MCG_STATUS_LMCES (1ULL<<3) /* LMCE signaled */
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/* MCG_EXT_CTL register defines */
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#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
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/* MCi_STATUS register defines */
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#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
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#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
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#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
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#define MCI_STATUS_AR (1ULL<<55) /* Action required */
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/* AMD-specific bits */
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#define MCI_STATUS_DEFERRED (1ULL<<44) /* declare an uncorrected error */
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#define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */
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/*
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* Note that the full MCACOD field of IA32_MCi_STATUS MSR is
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* bits 15:0. But bit 12 is the 'F' bit, defined for corrected
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* errors to indicate that errors are being filtered by hardware.
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* We should mask out bit 12 when looking for specific signatures
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* of uncorrected errors - so the F bit is deliberately skipped
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* in this #define.
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*/
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#define MCACOD 0xefff /* MCA Error Code */
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/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
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#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
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#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
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#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
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#define MCACOD_DATA 0x0134 /* Data Load */
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#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
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/* MCi_MISC register defines */
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#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
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#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
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#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
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#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
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#define MCI_MISC_ADDR_PHYS 2 /* physical address */
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#define MCI_MISC_ADDR_MEM 3 /* memory address */
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#define MCI_MISC_ADDR_GENERIC 7 /* generic */
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/* CTL2 register defines */
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#define MCI_CTL2_CMCI_EN (1ULL << 30)
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
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#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
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#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
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#define MCJ_EXCEPTION 0x8 /* raise as exception */
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#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
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#define MCE_LOG_LEN 32
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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* debugging tools. Each entry is only valid when its finished flag
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* is set.
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*/
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned recordlen; /* length of struct mce */
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struct mce entry[MCE_LOG_LEN];
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};
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struct mca_config {
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bool dont_log_ce;
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bool cmci_disabled;
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bool lmce_disabled;
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bool ignore_ce;
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bool disabled;
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bool ser;
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bool bios_cmci_threshold;
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u8 banks;
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s8 bootlog;
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int tolerant;
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int monarch_timeout;
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int panic_timeout;
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u32 rip_msr;
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};
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struct mce_vendor_flags {
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/*
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* Indicates that overflow conditions are not fatal, when set.
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*/
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__u64 overflow_recov : 1,
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/*
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* (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
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* Recovery. It indicates support for data poisoning in HW and deferred
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* error interrupts.
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*/
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succor : 1,
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/*
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* (AMD) SMCA: This bit indicates support for Scalable MCA which expands
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* the register space for each MCA bank and also increases number of
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* banks. Also, to accommodate the new banks and registers, the MCA
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* register space is moved to a new MSR range.
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*/
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smca : 1,
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__reserved_0 : 61;
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};
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extern struct mce_vendor_flags mce_flags;
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extern struct mca_config mca_cfg;
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extern void mce_register_decode_chain(struct notifier_block *nb);
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extern void mce_unregister_decode_chain(struct notifier_block *nb);
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#include <linux/percpu.h>
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#include <linux/atomic.h>
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extern int mce_p5_enabled;
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#ifdef CONFIG_X86_MCE
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int mcheck_init(void);
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void mcheck_cpu_init(struct cpuinfo_x86 *c);
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void mcheck_cpu_clear(struct cpuinfo_x86 *c);
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void mcheck_vendor_init_severity(void);
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#else
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static inline int mcheck_init(void) { return 0; }
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static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
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static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
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static inline void mcheck_vendor_init_severity(void) {}
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#endif
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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#else
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void enable_p5_mce(void) {}
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#endif
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void mce_setup(struct mce *m);
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct device *, mce_device);
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/*
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* Maximum banks number.
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* This is the limit of the current register layout on
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* Intel CPUs.
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*/
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#define MAX_NR_BANKS 32
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#ifdef CONFIG_X86_MCE_INTEL
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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void mce_intel_feature_clear(struct cpuinfo_x86 *c);
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void cmci_clear(void);
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void cmci_reenable(void);
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void cmci_rediscover(void);
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void cmci_recheck(void);
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#else
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
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static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
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static inline void cmci_clear(void) {}
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static inline void cmci_reenable(void) {}
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static inline void cmci_rediscover(void) {}
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static inline void cmci_recheck(void) {}
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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#endif
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int mce_available(struct cpuinfo_x86 *c);
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DECLARE_PER_CPU(unsigned, mce_exception_count);
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DECLARE_PER_CPU(unsigned, mce_poll_count);
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typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
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DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
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enum mcp_flags {
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MCP_TIMESTAMP = BIT(0), /* log time stamp */
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MCP_UC = BIT(1), /* log uncorrected errors */
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MCP_DONTLOG = BIT(2), /* only clear, don't log */
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};
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bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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int mce_notify_irq(void);
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DECLARE_PER_CPU(struct mce, injectm);
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extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
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const char __user *ubuf,
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size_t usize, loff_t *off));
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/* Disable CMCI/polling for MCA bank claimed by firmware */
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extern void mce_disable_bank(int bank);
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/*
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* Exception handler
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*/
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/* Call the installed machine check handler for this CPU setup. */
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extern void (*machine_check_vector)(struct pt_regs *, long error_code);
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void do_machine_check(struct pt_regs *, long);
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/*
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* Threshold handler
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*/
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extern void (*mce_threshold_vector)(void);
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extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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/* Deferred error interrupt handler */
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extern void (*deferred_error_int_vector)(void);
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/*
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* Thermal handler
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*/
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void intel_init_thermal(struct cpuinfo_x86 *c);
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void mce_log_therm_throt_event(__u64 status);
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/* Interrupt Handler for core thermal thresholds */
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extern int (*platform_thermal_notify)(__u64 msr_val);
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/* Interrupt Handler for package thermal thresholds */
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extern int (*platform_thermal_package_notify)(__u64 msr_val);
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/* Callback support of rate control, return true, if
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* callback has rate control */
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extern bool (*platform_thermal_package_rate_control)(void);
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#ifdef CONFIG_X86_THERMAL_VECTOR
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extern void mcheck_intel_therm_init(void);
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#else
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static inline void mcheck_intel_therm_init(void) { }
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#endif
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/*
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* Used by APEI to report memory error via /dev/mcelog
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*/
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struct cper_sec_mem_err;
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extern void apei_mce_report_mem_error(int corrected,
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struct cper_sec_mem_err *mem_err);
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#endif /* _ASM_X86_MCE_H */
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