mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-29 23:24:11 +08:00
5f7dc5d750
Unlike other alphas, marvel doesn't have real PC-style CMOS clock hardware - RTC accesses are emulated via PAL calls. Unfortunately, for unknown reason these calls work only on CPU #0. So current implementation for arbitrary CPU makes CMOS_READ/WRITE to be executed on CPU #0 via IPI. However, for obvious reason this doesn't work with standard get/set_rtc_time() functions, where a bunch of CMOS accesses is done with disabled interrupts. Solved by making the IPI calls for entire get/set_rtc_time() functions, not for individual CMOS accesses. Which is also a lot more effective performance-wise. The patch is largely based on the code from Jay Estabrook. My changes: - tweak asm-generic/rtc.h by adding a couple of #defines to avoid a massive code duplication in arch/alpha/include/asm/rtc.h; - sys_marvel.c: fix get/set_rtc_time() return values (Jay's FIXMEs). NOTE: this fixes *only* LIB_RTC drivers. Legacy (CONFIG_RTC) driver wont't work on marvel. Actually I think that we should just disable CONFIG_RTC on alpha (maybe in 2.6.30?), like most other arches - AFAIK, all modern distributions use LIB_RTC anyway. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
219 lines
5.3 KiB
C
219 lines
5.3 KiB
C
/*
|
|
* include/asm-generic/rtc.h
|
|
*
|
|
* Author: Tom Rini <trini@mvista.com>
|
|
*
|
|
* Based on:
|
|
* drivers/char/rtc.c
|
|
*
|
|
* Please read the COPYING file for all license details.
|
|
*/
|
|
|
|
#ifndef __ASM_RTC_H__
|
|
#define __ASM_RTC_H__
|
|
|
|
#include <linux/mc146818rtc.h>
|
|
#include <linux/rtc.h>
|
|
#include <linux/bcd.h>
|
|
#include <linux/delay.h>
|
|
|
|
#define RTC_PIE 0x40 /* periodic interrupt enable */
|
|
#define RTC_AIE 0x20 /* alarm interrupt enable */
|
|
#define RTC_UIE 0x10 /* update-finished interrupt enable */
|
|
|
|
/* some dummy definitions */
|
|
#define RTC_BATT_BAD 0x100 /* battery bad */
|
|
#define RTC_SQWE 0x08 /* enable square-wave output */
|
|
#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
|
|
#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
|
|
#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
|
|
|
|
/*
|
|
* Returns true if a clock update is in progress
|
|
*/
|
|
static inline unsigned char rtc_is_updating(void)
|
|
{
|
|
unsigned char uip;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&rtc_lock, flags);
|
|
uip = (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
|
|
spin_unlock_irqrestore(&rtc_lock, flags);
|
|
return uip;
|
|
}
|
|
|
|
static inline unsigned int __get_rtc_time(struct rtc_time *time)
|
|
{
|
|
unsigned char ctrl;
|
|
unsigned long flags;
|
|
|
|
#ifdef CONFIG_MACH_DECSTATION
|
|
unsigned int real_year;
|
|
#endif
|
|
|
|
/*
|
|
* read RTC once any update in progress is done. The update
|
|
* can take just over 2ms. We wait 20ms. There is no need to
|
|
* to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP.
|
|
* If you need to know *exactly* when a second has started, enable
|
|
* periodic update complete interrupts, (via ioctl) and then
|
|
* immediately read /dev/rtc which will block until you get the IRQ.
|
|
* Once the read clears, read the RTC time (again via ioctl). Easy.
|
|
*/
|
|
if (rtc_is_updating())
|
|
mdelay(20);
|
|
|
|
/*
|
|
* Only the values that we read from the RTC are set. We leave
|
|
* tm_wday, tm_yday and tm_isdst untouched. Even though the
|
|
* RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated
|
|
* by the RTC when initially set to a non-zero value.
|
|
*/
|
|
spin_lock_irqsave(&rtc_lock, flags);
|
|
time->tm_sec = CMOS_READ(RTC_SECONDS);
|
|
time->tm_min = CMOS_READ(RTC_MINUTES);
|
|
time->tm_hour = CMOS_READ(RTC_HOURS);
|
|
time->tm_mday = CMOS_READ(RTC_DAY_OF_MONTH);
|
|
time->tm_mon = CMOS_READ(RTC_MONTH);
|
|
time->tm_year = CMOS_READ(RTC_YEAR);
|
|
#ifdef CONFIG_MACH_DECSTATION
|
|
real_year = CMOS_READ(RTC_DEC_YEAR);
|
|
#endif
|
|
ctrl = CMOS_READ(RTC_CONTROL);
|
|
spin_unlock_irqrestore(&rtc_lock, flags);
|
|
|
|
if (!(ctrl & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
|
|
{
|
|
time->tm_sec = bcd2bin(time->tm_sec);
|
|
time->tm_min = bcd2bin(time->tm_min);
|
|
time->tm_hour = bcd2bin(time->tm_hour);
|
|
time->tm_mday = bcd2bin(time->tm_mday);
|
|
time->tm_mon = bcd2bin(time->tm_mon);
|
|
time->tm_year = bcd2bin(time->tm_year);
|
|
}
|
|
|
|
#ifdef CONFIG_MACH_DECSTATION
|
|
time->tm_year += real_year - 72;
|
|
#endif
|
|
|
|
/*
|
|
* Account for differences between how the RTC uses the values
|
|
* and how they are defined in a struct rtc_time;
|
|
*/
|
|
if (time->tm_year <= 69)
|
|
time->tm_year += 100;
|
|
|
|
time->tm_mon--;
|
|
|
|
return RTC_24H;
|
|
}
|
|
|
|
#ifndef get_rtc_time
|
|
#define get_rtc_time __get_rtc_time
|
|
#endif
|
|
|
|
/* Set the current date and time in the real time clock. */
|
|
static inline int __set_rtc_time(struct rtc_time *time)
|
|
{
|
|
unsigned long flags;
|
|
unsigned char mon, day, hrs, min, sec;
|
|
unsigned char save_control, save_freq_select;
|
|
unsigned int yrs;
|
|
#ifdef CONFIG_MACH_DECSTATION
|
|
unsigned int real_yrs, leap_yr;
|
|
#endif
|
|
|
|
yrs = time->tm_year;
|
|
mon = time->tm_mon + 1; /* tm_mon starts at zero */
|
|
day = time->tm_mday;
|
|
hrs = time->tm_hour;
|
|
min = time->tm_min;
|
|
sec = time->tm_sec;
|
|
|
|
if (yrs > 255) /* They are unsigned */
|
|
return -EINVAL;
|
|
|
|
spin_lock_irqsave(&rtc_lock, flags);
|
|
#ifdef CONFIG_MACH_DECSTATION
|
|
real_yrs = yrs;
|
|
leap_yr = ((!((yrs + 1900) % 4) && ((yrs + 1900) % 100)) ||
|
|
!((yrs + 1900) % 400));
|
|
yrs = 72;
|
|
|
|
/*
|
|
* We want to keep the year set to 73 until March
|
|
* for non-leap years, so that Feb, 29th is handled
|
|
* correctly.
|
|
*/
|
|
if (!leap_yr && mon < 3) {
|
|
real_yrs--;
|
|
yrs = 73;
|
|
}
|
|
#endif
|
|
/* These limits and adjustments are independent of
|
|
* whether the chip is in binary mode or not.
|
|
*/
|
|
if (yrs > 169) {
|
|
spin_unlock_irqrestore(&rtc_lock, flags);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (yrs >= 100)
|
|
yrs -= 100;
|
|
|
|
if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
|
|
|| RTC_ALWAYS_BCD) {
|
|
sec = bin2bcd(sec);
|
|
min = bin2bcd(min);
|
|
hrs = bin2bcd(hrs);
|
|
day = bin2bcd(day);
|
|
mon = bin2bcd(mon);
|
|
yrs = bin2bcd(yrs);
|
|
}
|
|
|
|
save_control = CMOS_READ(RTC_CONTROL);
|
|
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
|
|
save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
|
|
CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
|
|
|
|
#ifdef CONFIG_MACH_DECSTATION
|
|
CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
|
|
#endif
|
|
CMOS_WRITE(yrs, RTC_YEAR);
|
|
CMOS_WRITE(mon, RTC_MONTH);
|
|
CMOS_WRITE(day, RTC_DAY_OF_MONTH);
|
|
CMOS_WRITE(hrs, RTC_HOURS);
|
|
CMOS_WRITE(min, RTC_MINUTES);
|
|
CMOS_WRITE(sec, RTC_SECONDS);
|
|
|
|
CMOS_WRITE(save_control, RTC_CONTROL);
|
|
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
|
|
|
|
spin_unlock_irqrestore(&rtc_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifndef set_rtc_time
|
|
#define set_rtc_time __set_rtc_time
|
|
#endif
|
|
|
|
static inline unsigned int get_rtc_ss(void)
|
|
{
|
|
struct rtc_time h;
|
|
|
|
__get_rtc_time(&h);
|
|
return h.tm_sec;
|
|
}
|
|
|
|
static inline int get_rtc_pll(struct rtc_pll_info *pll)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
static inline int set_rtc_pll(struct rtc_pll_info *pll)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
#endif /* __ASM_RTC_H__ */
|