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2a434f2471
Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx devicetree files: * added dts file for MYIR Tech MYD-LPC4357 development board, * two missing properties are added to LPC32xx keypad controller device tree node, this fixes a long-standing problem with its initialization, * LPC32xx PL11x LCD controller device node got corrected properties, which allows to use it with a new PL11x DRM driver, * output voltage level on one of Phytec phyCORE-LPC3250 fixed regulators is corrected, the fix is needed to remove duplicating platform data, * Phytec phyCORE-LPC3250 board gets a description of a kit LCD panel, this completes setup of CLCD device tree node for the board, * added unit addresses to memory device nodes on EA and Phytec boards, * fixes of ordinary warnings in dts formatting like leading zeroes, unused address and size cell properties and so on. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEETKMJMWSwX7CFTVIOqj3i2jwlOWUFAlxXTzIACgkQqj3i2jwl OWXBRA//RCAfC/GhIyZF1uHIhj/G85sAWuGSYQ90+fEVtyzb1Y+yeBRKkNH2Xi8C LkSzD58z/1BTaYz68EaRENU3xCkBcBHH8ZymqJP8/pG+/AoLVIg7/wkeFj/BCC80 rESTV4IjTFdbAaqmM8Y/rcWuPTs5fgxZzFdCgqY0FuTee5hx5aLQkA39cIPWJLJz Ox+e/Yhs00blWZUFyitP5sd/rnVeuNXWqY0VnN8hG4oH4+GJOA8QAIzzq1DTKaj0 43073ymRw4ZOry0qfsbRvjQZwvSAQD+kZx24DXwP+6YFdW8DqdAZPkuCYYMV10JO tiOg6hHHjM1lKJWom/6N1Z9layMZeyPxBRYQ2Tpn3+5Or05iHgAhbYv5kRvIBZ8W cL8hA9SNb/g4yRa67GBINdGHlf3nRBvqDgOR0OQEF3Q/JTFferJOb3MhGuIX1fS7 39JRIndLJD10SoK/Nezvc68myei8aQ+YTQBzaNkm3q4q4SuLF9nEb92s313yvzKv vBwMuaGuTL+pBvDR3qGsFHxrExj1DIbecYqGdvGj0lmSZbNPWeR2ZSj6XGfT18x3 pCmr7C6brY6jWsp6p8nG7ovFkPqv3X3x/gBszLFGFaEedkssabfLesWdZooHIAgJ Fa6Lc2M7AAwxHT1YDn6+ojrr/yhaQoaray/+aOT9WAwAhElpc24= =J1uJ -----END PGP SIGNATURE----- Merge tag 'lpc32xx-dt-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx into arm/dt ARM: lpc32xx: devicetree updates for v5.1 Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx devicetree files: * added dts file for MYIR Tech MYD-LPC4357 development board, * two missing properties are added to LPC32xx keypad controller device tree node, this fixes a long-standing problem with its initialization, * LPC32xx PL11x LCD controller device node got corrected properties, which allows to use it with a new PL11x DRM driver, * output voltage level on one of Phytec phyCORE-LPC3250 fixed regulators is corrected, the fix is needed to remove duplicating platform data, * Phytec phyCORE-LPC3250 board gets a description of a kit LCD panel, this completes setup of CLCD device tree node for the board, * added unit addresses to memory device nodes on EA and Phytec boards, * fixes of ordinary warnings in dts formatting like leading zeroes, unused address and size cell properties and so on. * tag 'lpc32xx-dt-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx: ARM: dts: lpc32xx: ea3250: beautify gpio keys children nodes ARM: dts: lpc32xx: ea3250: add unit address to memory device node ARM: dts: lpc32xx: phy3250: add unit address to memory device node ARM: dts: lpc32xx: phy3250: setup LCD controller to panel interface ARM: dts: lpc32xx: phy3250: remove regulators umbrella device node ARM: dts: lpc32xx: phy3250: fix SD card regulator voltage ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller clocks property ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller variant ARM: dts: lpc32xx: reparent keypad controller to SIC1 ARM: dts: lpc32xx: add required clocks property to keypad device node ARM: dts: Add DT for MYIR Tech MYD-LPC4357 Development Board ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notation ARM: dts: lpc435x: remove address and size cells from gpio-keys-polled nodes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
509 lines
12 KiB
Plaintext
509 lines
12 KiB
Plaintext
/*
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* NXP LPC32xx SoC
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*
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* Copyright 2012 Roland Stigge <stigge@antcom.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <dt-bindings/clock/lpc32xx-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "nxp,lpc3220";
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interrupt-parent = <&mic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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reg = <0x0>;
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};
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};
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clocks {
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xtal_32k: xtal_32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xtal_32k";
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};
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xtal: xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <13000000>;
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clock-output-names = "xtal";
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};
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};
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ahb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x00000000 0x00000000 0x10000000>,
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<0x20000000 0x20000000 0x30000000>,
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<0xe0000000 0xe0000000 0x04000000>;
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iram: sram@8000000 {
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compatible = "mmio-sram";
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reg = <0x08000000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x08000000 0x20000>;
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};
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/*
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* Enable either SLC or MLC
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*/
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slc: flash@20020000 {
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compatible = "nxp,lpc3220-slc";
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reg = <0x20020000 0x1000>;
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clocks = <&clk LPC32XX_CLK_SLC>;
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status = "disabled";
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};
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mlc: flash@200a8000 {
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compatible = "nxp,lpc3220-mlc";
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reg = <0x200a8000 0x11000>;
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interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_MLC>;
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status = "disabled";
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};
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dma: dma@31000000 {
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compatible = "arm,pl080", "arm,primecell";
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reg = <0x31000000 0x1000>;
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interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_DMA>;
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clock-names = "apb_pclk";
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};
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usb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x31020000 0x00001000>;
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/*
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* Enable either ohci or usbd (gadget)!
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*/
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ohci: ohci@0 {
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compatible = "nxp,ohci-nxp", "usb-ohci";
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reg = <0x0 0x300>;
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interrupt-parent = <&sic1>;
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interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
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status = "disabled";
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};
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usbd: usbd@0 {
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compatible = "nxp,lpc3220-udc";
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reg = <0x0 0x300>;
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interrupt-parent = <&sic1>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
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<30 IRQ_TYPE_LEVEL_HIGH>,
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<28 IRQ_TYPE_LEVEL_HIGH>,
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<26 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
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status = "disabled";
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};
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i2cusb: i2c@300 {
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compatible = "nxp,pnx-i2c";
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reg = <0x300 0x100>;
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interrupt-parent = <&sic1>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
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#address-cells = <1>;
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#size-cells = <0>;
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pnx,timeout = <0x64>;
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};
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usbclk: clock-controller@f00 {
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compatible = "nxp,lpc3220-usb-clk";
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reg = <0xf00 0x100>;
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#clock-cells = <1>;
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};
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};
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clcd: clcd@31040000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x31040000 0x1000>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
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clock-names = "clcdclk", "apb_pclk";
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status = "disabled";
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};
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mac: ethernet@31060000 {
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compatible = "nxp,lpc-eth";
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reg = <0x31060000 0x1000>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_MAC>;
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};
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emc: memory-controller@31080000 {
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compatible = "arm,pl175", "arm,primecell";
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reg = <0x31080000 0x1000>;
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clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
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clock-names = "mpmcclk", "apb_pclk";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe0000000 0x01000000>,
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<1 0xe1000000 0x01000000>,
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<2 0xe2000000 0x01000000>,
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<3 0xe3000000 0x01000000>;
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status = "disabled";
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};
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apb {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x20000000 0x20000000 0x30000000>;
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/*
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* ssp0 and spi1 are shared pins;
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* enable one in your board dts, as needed.
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*/
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ssp0: spi@20084000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x20084000 0x1000>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_SSP0>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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spi1: spi@20088000 {
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compatible = "nxp,lpc3220-spi";
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reg = <0x20088000 0x1000>;
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clocks = <&clk LPC32XX_CLK_SPI1>;
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status = "disabled";
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};
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/*
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* ssp1 and spi2 are shared pins;
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* enable one in your board dts, as needed.
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*/
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ssp1: spi@2008c000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x2008c000 0x1000>;
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interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_SSP1>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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spi2: spi@20090000 {
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compatible = "nxp,lpc3220-spi";
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reg = <0x20090000 0x1000>;
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clocks = <&clk LPC32XX_CLK_SPI2>;
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status = "disabled";
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};
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i2s0: i2s@20094000 {
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compatible = "nxp,lpc3220-i2s";
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reg = <0x20094000 0x1000>;
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};
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sd: sd@20098000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x20098000 0x1000>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
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<13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_SD>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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i2s1: i2s@2009c000 {
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compatible = "nxp,lpc3220-i2s";
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reg = <0x2009C000 0x1000>;
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};
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/* UART5 first since it is the default console, ttyS0 */
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uart5: serial@40090000 {
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/* actually, ns16550a w/ 64 byte fifos! */
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compatible = "nxp,lpc3220-uart";
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reg = <0x40090000 0x1000>;
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interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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clocks = <&clk LPC32XX_CLK_UART5>;
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status = "disabled";
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};
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uart3: serial@40080000 {
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compatible = "nxp,lpc3220-uart";
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reg = <0x40080000 0x1000>;
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interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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clocks = <&clk LPC32XX_CLK_UART3>;
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status = "disabled";
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};
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uart4: serial@40088000 {
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compatible = "nxp,lpc3220-uart";
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reg = <0x40088000 0x1000>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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clocks = <&clk LPC32XX_CLK_UART4>;
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status = "disabled";
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};
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uart6: serial@40098000 {
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compatible = "nxp,lpc3220-uart";
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reg = <0x40098000 0x1000>;
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interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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clocks = <&clk LPC32XX_CLK_UART6>;
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status = "disabled";
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};
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i2c1: i2c@400a0000 {
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compatible = "nxp,pnx-i2c";
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reg = <0x400A0000 0x100>;
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interrupt-parent = <&sic1>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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#address-cells = <1>;
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#size-cells = <0>;
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pnx,timeout = <0x64>;
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clocks = <&clk LPC32XX_CLK_I2C1>;
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};
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i2c2: i2c@400a8000 {
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compatible = "nxp,pnx-i2c";
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reg = <0x400A8000 0x100>;
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interrupt-parent = <&sic1>;
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interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
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#address-cells = <1>;
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#size-cells = <0>;
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pnx,timeout = <0x64>;
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clocks = <&clk LPC32XX_CLK_I2C2>;
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};
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mpwm: mpwm@400e8000 {
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compatible = "nxp,lpc3220-motor-pwm";
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reg = <0x400E8000 0x78>;
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status = "disabled";
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#pwm-cells = <2>;
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};
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};
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fab {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x20000000 0x20000000 0x30000000>;
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/* System Control Block */
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scb {
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compatible = "simple-bus";
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ranges = <0x0 0x040004000 0x00001000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clk: clock-controller@0 {
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compatible = "nxp,lpc3220-clk";
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reg = <0x00 0x114>;
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#clock-cells = <1>;
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clocks = <&xtal_32k>, <&xtal>;
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clock-names = "xtal_32k", "xtal";
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assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
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assigned-clock-rates = <208000000>;
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};
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};
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mic: interrupt-controller@40008000 {
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compatible = "nxp,lpc3220-mic";
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reg = <0x40008000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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sic1: interrupt-controller@4000c000 {
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compatible = "nxp,lpc3220-sic";
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reg = <0x4000c000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&mic>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
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<30 IRQ_TYPE_LEVEL_LOW>;
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};
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sic2: interrupt-controller@40010000 {
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compatible = "nxp,lpc3220-sic";
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reg = <0x40010000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&mic>;
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
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<31 IRQ_TYPE_LEVEL_LOW>;
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};
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uart1: serial@40014000 {
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compatible = "nxp,lpc3220-hsuart";
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reg = <0x40014000 0x1000>;
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interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart2: serial@40018000 {
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compatible = "nxp,lpc3220-hsuart";
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reg = <0x40018000 0x1000>;
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interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart7: serial@4001c000 {
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compatible = "nxp,lpc3220-hsuart";
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reg = <0x4001c000 0x1000>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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rtc: rtc@40024000 {
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compatible = "nxp,lpc3220-rtc";
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reg = <0x40024000 0x1000>;
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interrupt-parent = <&sic1>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk LPC32XX_CLK_RTC>;
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};
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gpio: gpio@40028000 {
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compatible = "nxp,lpc3220-gpio";
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reg = <0x40028000 0x1000>;
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gpio-controller;
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#gpio-cells = <3>; /* bank, pin, flags */
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};
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timer4: timer@4002c000 {
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compatible = "nxp,lpc3220-timer";
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reg = <0x4002C000 0x1000>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&clk LPC32XX_CLK_TIMER4>;
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clock-names = "timerclk";
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status = "disabled";
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};
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timer5: timer@40030000 {
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compatible = "nxp,lpc3220-timer";
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reg = <0x40030000 0x1000>;
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&clk LPC32XX_CLK_TIMER5>;
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clock-names = "timerclk";
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status = "disabled";
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};
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watchdog: watchdog@4003c000 {
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compatible = "nxp,pnx4008-wdt";
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reg = <0x4003C000 0x1000>;
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clocks = <&clk LPC32XX_CLK_WDOG>;
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};
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|
|
|
timer0: timer@40044000 {
|
|
compatible = "nxp,lpc3220-timer";
|
|
reg = <0x40044000 0x1000>;
|
|
clocks = <&clk LPC32XX_CLK_TIMER0>;
|
|
clock-names = "timerclk";
|
|
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
/*
|
|
* TSC vs. ADC: Since those two share the same
|
|
* hardware, you need to choose from one of the
|
|
* following two and do 'status = "okay";' for one of
|
|
* them
|
|
*/
|
|
|
|
adc: adc@40048000 {
|
|
compatible = "nxp,lpc3220-adc";
|
|
reg = <0x40048000 0x1000>;
|
|
interrupt-parent = <&sic1>;
|
|
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk LPC32XX_CLK_ADC>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tsc: tsc@40048000 {
|
|
compatible = "nxp,lpc3220-tsc";
|
|
reg = <0x40048000 0x1000>;
|
|
interrupt-parent = <&sic1>;
|
|
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk LPC32XX_CLK_ADC>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer1: timer@4004c000 {
|
|
compatible = "nxp,lpc3220-timer";
|
|
reg = <0x4004C000 0x1000>;
|
|
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk LPC32XX_CLK_TIMER1>;
|
|
clock-names = "timerclk";
|
|
};
|
|
|
|
key: key@40050000 {
|
|
compatible = "nxp,lpc3220-key";
|
|
reg = <0x40050000 0x1000>;
|
|
clocks = <&clk LPC32XX_CLK_KEY>;
|
|
interrupt-parent = <&sic1>;
|
|
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer2: timer@40058000 {
|
|
compatible = "nxp,lpc3220-timer";
|
|
reg = <0x40058000 0x1000>;
|
|
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk LPC32XX_CLK_TIMER2>;
|
|
clock-names = "timerclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@4005c000 {
|
|
compatible = "nxp,lpc3220-pwm";
|
|
reg = <0x4005C000 0x4>;
|
|
clocks = <&clk LPC32XX_CLK_PWM1>;
|
|
assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
|
|
assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@4005c004 {
|
|
compatible = "nxp,lpc3220-pwm";
|
|
reg = <0x4005C004 0x4>;
|
|
clocks = <&clk LPC32XX_CLK_PWM2>;
|
|
assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
|
|
assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer3: timer@40060000 {
|
|
compatible = "nxp,lpc3220-timer";
|
|
reg = <0x40060000 0x1000>;
|
|
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk LPC32XX_CLK_TIMER3>;
|
|
clock-names = "timerclk";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|