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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
231 lines
7.1 KiB
C
231 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 ARM Ltd.
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*/
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#ifndef __ASM_PERCPU_H
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#define __ASM_PERCPU_H
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#include <linux/preempt.h>
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#include <asm/alternative.h>
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#include <asm/cmpxchg.h>
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#include <asm/stack_pointer.h>
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static inline void set_my_cpu_offset(unsigned long off)
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{
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asm volatile(ALTERNATIVE("msr tpidr_el1, %0",
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"msr tpidr_el2, %0",
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ARM64_HAS_VIRT_HOST_EXTN)
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:: "r" (off) : "memory");
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}
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static inline unsigned long __my_cpu_offset(void)
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{
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unsigned long off;
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/*
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* We want to allow caching the value, so avoid using volatile and
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* instead use a fake stack read to hazard against barrier().
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*/
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asm(ALTERNATIVE("mrs %0, tpidr_el1",
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"mrs %0, tpidr_el2",
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ARM64_HAS_VIRT_HOST_EXTN)
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: "=r" (off) :
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"Q" (*(const unsigned long *)current_stack_pointer));
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return off;
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}
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#define __my_cpu_offset __my_cpu_offset()
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#define PERCPU_RW_OPS(sz) \
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static inline unsigned long __percpu_read_##sz(void *ptr) \
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{ \
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return READ_ONCE(*(u##sz *)ptr); \
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} \
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\
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static inline void __percpu_write_##sz(void *ptr, unsigned long val) \
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{ \
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WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \
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}
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#define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \
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static inline void \
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__percpu_##name##_case_##sz(void *ptr, unsigned long val) \
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{ \
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unsigned int loop; \
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u##sz tmp; \
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\
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asm volatile (ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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"1: ldxr" #sfx "\t%" #w "[tmp], %[ptr]\n" \
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#op_llsc "\t%" #w "[tmp], %" #w "[tmp], %" #w "[val]\n" \
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" stxr" #sfx "\t%w[loop], %" #w "[tmp], %[ptr]\n" \
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" cbnz %w[loop], 1b", \
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/* LSE atomics */ \
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#op_lse "\t%" #w "[val], %[ptr]\n" \
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__nops(3)) \
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: [loop] "=&r" (loop), [tmp] "=&r" (tmp), \
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[ptr] "+Q"(*(u##sz *)ptr) \
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: [val] "r" ((u##sz)(val))); \
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}
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#define __PERCPU_RET_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \
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static inline u##sz \
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__percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \
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{ \
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unsigned int loop; \
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u##sz ret; \
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\
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asm volatile (ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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"1: ldxr" #sfx "\t%" #w "[ret], %[ptr]\n" \
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#op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \
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" stxr" #sfx "\t%w[loop], %" #w "[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b", \
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/* LSE atomics */ \
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#op_lse "\t%" #w "[val], %" #w "[ret], %[ptr]\n" \
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#op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \
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__nops(2)) \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u##sz *)ptr) \
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: [val] "r" ((u##sz)(val))); \
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\
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return ret; \
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}
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#define PERCPU_OP(name, op_llsc, op_lse) \
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__PERCPU_OP_CASE(w, b, name, 8, op_llsc, op_lse) \
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__PERCPU_OP_CASE(w, h, name, 16, op_llsc, op_lse) \
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__PERCPU_OP_CASE(w, , name, 32, op_llsc, op_lse) \
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__PERCPU_OP_CASE( , , name, 64, op_llsc, op_lse)
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#define PERCPU_RET_OP(name, op_llsc, op_lse) \
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__PERCPU_RET_OP_CASE(w, b, name, 8, op_llsc, op_lse) \
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__PERCPU_RET_OP_CASE(w, h, name, 16, op_llsc, op_lse) \
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__PERCPU_RET_OP_CASE(w, , name, 32, op_llsc, op_lse) \
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__PERCPU_RET_OP_CASE( , , name, 64, op_llsc, op_lse)
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PERCPU_RW_OPS(8)
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PERCPU_RW_OPS(16)
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PERCPU_RW_OPS(32)
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PERCPU_RW_OPS(64)
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PERCPU_OP(add, add, stadd)
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PERCPU_OP(andnot, bic, stclr)
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PERCPU_OP(or, orr, stset)
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PERCPU_RET_OP(add, add, ldadd)
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#undef PERCPU_RW_OPS
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#undef __PERCPU_OP_CASE
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#undef __PERCPU_RET_OP_CASE
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#undef PERCPU_OP
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#undef PERCPU_RET_OP
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/*
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* It would be nice to avoid the conditional call into the scheduler when
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* re-enabling preemption for preemptible kernels, but doing that in a way
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* which builds inside a module would mean messing directly with the preempt
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* count. If you do this, peterz and tglx will hunt you down.
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*/
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#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \
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({ \
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int __ret; \
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preempt_disable_notrace(); \
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__ret = cmpxchg_double_local( raw_cpu_ptr(&(ptr1)), \
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raw_cpu_ptr(&(ptr2)), \
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o1, o2, n1, n2); \
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preempt_enable_notrace(); \
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__ret; \
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})
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#define _pcp_protect(op, pcp, ...) \
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({ \
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preempt_disable_notrace(); \
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op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); \
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preempt_enable_notrace(); \
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})
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#define _pcp_protect_return(op, pcp, args...) \
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({ \
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typeof(pcp) __retval; \
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preempt_disable_notrace(); \
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__retval = (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args); \
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preempt_enable_notrace(); \
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__retval; \
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})
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#define this_cpu_read_1(pcp) \
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_pcp_protect_return(__percpu_read_8, pcp)
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#define this_cpu_read_2(pcp) \
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_pcp_protect_return(__percpu_read_16, pcp)
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#define this_cpu_read_4(pcp) \
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_pcp_protect_return(__percpu_read_32, pcp)
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#define this_cpu_read_8(pcp) \
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_pcp_protect_return(__percpu_read_64, pcp)
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#define this_cpu_write_1(pcp, val) \
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_pcp_protect(__percpu_write_8, pcp, (unsigned long)val)
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#define this_cpu_write_2(pcp, val) \
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_pcp_protect(__percpu_write_16, pcp, (unsigned long)val)
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#define this_cpu_write_4(pcp, val) \
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_pcp_protect(__percpu_write_32, pcp, (unsigned long)val)
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#define this_cpu_write_8(pcp, val) \
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_pcp_protect(__percpu_write_64, pcp, (unsigned long)val)
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#define this_cpu_add_1(pcp, val) \
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_pcp_protect(__percpu_add_case_8, pcp, val)
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#define this_cpu_add_2(pcp, val) \
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_pcp_protect(__percpu_add_case_16, pcp, val)
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#define this_cpu_add_4(pcp, val) \
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_pcp_protect(__percpu_add_case_32, pcp, val)
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#define this_cpu_add_8(pcp, val) \
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_pcp_protect(__percpu_add_case_64, pcp, val)
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#define this_cpu_add_return_1(pcp, val) \
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_pcp_protect_return(__percpu_add_return_case_8, pcp, val)
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#define this_cpu_add_return_2(pcp, val) \
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_pcp_protect_return(__percpu_add_return_case_16, pcp, val)
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#define this_cpu_add_return_4(pcp, val) \
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_pcp_protect_return(__percpu_add_return_case_32, pcp, val)
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#define this_cpu_add_return_8(pcp, val) \
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_pcp_protect_return(__percpu_add_return_case_64, pcp, val)
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#define this_cpu_and_1(pcp, val) \
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_pcp_protect(__percpu_andnot_case_8, pcp, ~val)
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#define this_cpu_and_2(pcp, val) \
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_pcp_protect(__percpu_andnot_case_16, pcp, ~val)
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#define this_cpu_and_4(pcp, val) \
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_pcp_protect(__percpu_andnot_case_32, pcp, ~val)
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#define this_cpu_and_8(pcp, val) \
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_pcp_protect(__percpu_andnot_case_64, pcp, ~val)
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#define this_cpu_or_1(pcp, val) \
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_pcp_protect(__percpu_or_case_8, pcp, val)
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#define this_cpu_or_2(pcp, val) \
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_pcp_protect(__percpu_or_case_16, pcp, val)
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#define this_cpu_or_4(pcp, val) \
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_pcp_protect(__percpu_or_case_32, pcp, val)
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#define this_cpu_or_8(pcp, val) \
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_pcp_protect(__percpu_or_case_64, pcp, val)
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#define this_cpu_xchg_1(pcp, val) \
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_pcp_protect_return(xchg_relaxed, pcp, val)
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#define this_cpu_xchg_2(pcp, val) \
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_pcp_protect_return(xchg_relaxed, pcp, val)
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#define this_cpu_xchg_4(pcp, val) \
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_pcp_protect_return(xchg_relaxed, pcp, val)
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#define this_cpu_xchg_8(pcp, val) \
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_pcp_protect_return(xchg_relaxed, pcp, val)
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#define this_cpu_cmpxchg_1(pcp, o, n) \
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_pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
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#define this_cpu_cmpxchg_2(pcp, o, n) \
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_pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
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#define this_cpu_cmpxchg_4(pcp, o, n) \
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_pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
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#define this_cpu_cmpxchg_8(pcp, o, n) \
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_pcp_protect_return(cmpxchg_relaxed, pcp, o, n)
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#include <asm-generic/percpu.h>
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#endif /* __ASM_PERCPU_H */
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