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Add support for Qualcomm Inline Crypto Engine (ICE) to ufs-qcom.
The standards-compliant parts, such as querying the crypto capabilities and
enabling crypto for individual UFS requests, are already handled by
ufshcd-crypto.c, which itself is wired into the blk-crypto framework.
However, ICE requires vendor-specific init, enable, and resume logic, and
it requires that keys be programmed and evicted by vendor-specific SMC
calls. Make the ufs-qcom driver handle these details.
I tested this on Dragonboard 845c, which is a publicly available
development board that uses the Snapdragon 845 SoC and runs the upstream
Linux kernel. This is the same SoC used in the Pixel 3 and Pixel 3 XL
phones. This testing included (among other things) verifying that the
expected ciphertext was produced, both manually using ext4 encryption and
automatically using a block layer self-test I've written.
I've also tested that this driver works nearly as-is on the Snapdragon 765
and Snapdragon 865 SoCs. And others have tested it on Snapdragon 850,
Snapdragon 855, and Snapdragon 865 (see the Tested-by tags).
This is based very loosely on the vendor-provided driver in the kernel
source code for the Pixel 3, but I've greatly simplified it. Also, for now
I've only included support for major version 3 of ICE, since that's all I
have the hardware to test with the mainline kernel. Plus it appears that
version 3 is easier to use than older versions of ICE.
For now, only allow using AES-256-XTS. The hardware also declares support
for AES-128-XTS, AES-{128,256}-ECB, and AES-{128,256}-CBC (BitLocker
variant). But none of these others are really useful, and they'd need to
be individually tested to be sure they worked properly.
This commit also changes the name of the loadable module from "ufs-qcom" to
"ufs_qcom", as this is necessary to compile it from multiple source files
(unless we were to rename ufs-qcom.c).
Link: https://lore.kernel.org/r/20200710072013.177481-6-ebiggers@kernel.org
Tested-by: Steev Klimaszewski <steev@kali.org> # Lenovo Yoga C630
Tested-by: Thara Gopinath <thara.gopinath@linaro.org> # db845c, sm8150-mtp, sm8250-mtp
Reviewed-by: Avri Altman <avri.altman@wdc.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
246 lines
6.6 KiB
C
246 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Qualcomm ICE (Inline Crypto Engine) support.
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*
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* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
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* Copyright 2019 Google LLC
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*/
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#include <linux/platform_device.h>
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#include <linux/qcom_scm.h>
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#include "ufshcd-crypto.h"
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#include "ufs-qcom.h"
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#define AES_256_XTS_KEY_SIZE 64
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/* QCOM ICE registers */
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#define QCOM_ICE_REG_CONTROL 0x0000
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#define QCOM_ICE_REG_RESET 0x0004
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#define QCOM_ICE_REG_VERSION 0x0008
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#define QCOM_ICE_REG_FUSE_SETTING 0x0010
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#define QCOM_ICE_REG_PARAMETERS_1 0x0014
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#define QCOM_ICE_REG_PARAMETERS_2 0x0018
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#define QCOM_ICE_REG_PARAMETERS_3 0x001C
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#define QCOM_ICE_REG_PARAMETERS_4 0x0020
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#define QCOM_ICE_REG_PARAMETERS_5 0x0024
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/* QCOM ICE v3.X only */
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#define QCOM_ICE_GENERAL_ERR_STTS 0x0040
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#define QCOM_ICE_INVALID_CCFG_ERR_STTS 0x0030
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#define QCOM_ICE_GENERAL_ERR_MASK 0x0044
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/* QCOM ICE v2.X only */
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#define QCOM_ICE_REG_NON_SEC_IRQ_STTS 0x0040
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#define QCOM_ICE_REG_NON_SEC_IRQ_MASK 0x0044
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#define QCOM_ICE_REG_NON_SEC_IRQ_CLR 0x0048
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#define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME1 0x0050
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#define QCOM_ICE_REG_STREAM1_ERROR_SYNDROME2 0x0054
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#define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME1 0x0058
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#define QCOM_ICE_REG_STREAM2_ERROR_SYNDROME2 0x005C
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#define QCOM_ICE_REG_STREAM1_BIST_ERROR_VEC 0x0060
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#define QCOM_ICE_REG_STREAM2_BIST_ERROR_VEC 0x0064
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#define QCOM_ICE_REG_STREAM1_BIST_FINISH_VEC 0x0068
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#define QCOM_ICE_REG_STREAM2_BIST_FINISH_VEC 0x006C
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#define QCOM_ICE_REG_BIST_STATUS 0x0070
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#define QCOM_ICE_REG_BYPASS_STATUS 0x0074
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#define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000
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#define QCOM_ICE_REG_ENDIAN_SWAP 0x1004
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#define QCOM_ICE_REG_TEST_BUS_CONTROL 0x1010
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#define QCOM_ICE_REG_TEST_BUS_REG 0x1014
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/* BIST ("built-in self-test"?) status flags */
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#define QCOM_ICE_BIST_STATUS_MASK 0xF0000000
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#define QCOM_ICE_FUSE_SETTING_MASK 0x1
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#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2
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#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4
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#define qcom_ice_writel(host, val, reg) \
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writel((val), (host)->ice_mmio + (reg))
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#define qcom_ice_readl(host, reg) \
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readl((host)->ice_mmio + (reg))
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static bool qcom_ice_supported(struct ufs_qcom_host *host)
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{
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struct device *dev = host->hba->dev;
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u32 regval = qcom_ice_readl(host, QCOM_ICE_REG_VERSION);
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int major = regval >> 24;
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int minor = (regval >> 16) & 0xFF;
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int step = regval & 0xFFFF;
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/* For now this driver only supports ICE version 3. */
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if (major != 3) {
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dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n",
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major, minor, step);
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return false;
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}
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dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
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major, minor, step);
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/* If fuses are blown, ICE might not work in the standard way. */
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regval = qcom_ice_readl(host, QCOM_ICE_REG_FUSE_SETTING);
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if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
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QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK |
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QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) {
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dev_warn(dev, "Fuses are blown; ICE is unusable!\n");
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return false;
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}
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return true;
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}
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int ufs_qcom_ice_init(struct ufs_qcom_host *host)
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{
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struct ufs_hba *hba = host->hba;
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struct device *dev = hba->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res;
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int err;
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if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) &
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MASK_CRYPTO_SUPPORT))
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return 0;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice");
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if (!res) {
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dev_warn(dev, "ICE registers not found\n");
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goto disable;
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}
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if (!qcom_scm_ice_available()) {
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dev_warn(dev, "ICE SCM interface not found\n");
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goto disable;
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}
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host->ice_mmio = devm_ioremap_resource(dev, res);
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if (IS_ERR(host->ice_mmio)) {
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err = PTR_ERR(host->ice_mmio);
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dev_err(dev, "Failed to map ICE registers; err=%d\n", err);
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return err;
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}
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if (!qcom_ice_supported(host))
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goto disable;
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return 0;
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disable:
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dev_warn(dev, "Disabling inline encryption support\n");
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hba->caps &= ~UFSHCD_CAP_CRYPTO;
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return 0;
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}
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static void qcom_ice_low_power_mode_enable(struct ufs_qcom_host *host)
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{
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u32 regval;
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regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);
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/*
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* Enable low power mode sequence
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* [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0
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*/
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regval |= 0x7000;
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qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
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}
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static void qcom_ice_optimization_enable(struct ufs_qcom_host *host)
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{
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u32 regval;
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/* ICE Optimizations Enable Sequence */
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regval = qcom_ice_readl(host, QCOM_ICE_REG_ADVANCED_CONTROL);
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regval |= 0xD807100;
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/* ICE HPG requires delay before writing */
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udelay(5);
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qcom_ice_writel(host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
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udelay(5);
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}
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int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
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{
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if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))
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return 0;
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qcom_ice_low_power_mode_enable(host);
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qcom_ice_optimization_enable(host);
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return ufs_qcom_ice_resume(host);
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}
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/* Poll until all BIST bits are reset */
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static int qcom_ice_wait_bist_status(struct ufs_qcom_host *host)
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{
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int count;
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u32 reg;
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for (count = 0; count < 100; count++) {
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reg = qcom_ice_readl(host, QCOM_ICE_REG_BIST_STATUS);
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if (!(reg & QCOM_ICE_BIST_STATUS_MASK))
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break;
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udelay(50);
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}
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if (reg)
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return -ETIMEDOUT;
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return 0;
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}
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int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
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{
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int err;
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if (!(host->hba->caps & UFSHCD_CAP_CRYPTO))
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return 0;
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err = qcom_ice_wait_bist_status(host);
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if (err) {
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dev_err(host->hba->dev, "BIST status error (%d)\n", err);
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return err;
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}
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return 0;
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}
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/*
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* Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires
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* vendor-specific SCM calls for this; it doesn't support the standard way.
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*/
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int ufs_qcom_ice_program_key(struct ufs_hba *hba,
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const union ufs_crypto_cfg_entry *cfg, int slot)
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{
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union ufs_crypto_cap_entry cap;
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union {
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u8 bytes[AES_256_XTS_KEY_SIZE];
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u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
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} key;
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int i;
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int err;
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if (!(cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE))
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return qcom_scm_ice_invalidate_key(slot);
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/* Only AES-256-XTS has been tested so far. */
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cap = hba->crypto_cap_array[cfg->crypto_cap_idx];
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if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS ||
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cap.key_size != UFS_CRYPTO_KEY_SIZE_256) {
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dev_err_ratelimited(hba->dev,
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"Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
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cap.algorithm_id, cap.key_size);
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return -EINVAL;
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}
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memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE);
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/*
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* The SCM call byte-swaps the 32-bit words of the key. So we have to
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* do the same, in order for the final key be correct.
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*/
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for (i = 0; i < ARRAY_SIZE(key.words); i++)
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__cpu_to_be32s(&key.words[i]);
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err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
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QCOM_SCM_ICE_CIPHER_AES_256_XTS,
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cfg->data_unit_size);
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memzero_explicit(&key, sizeof(key));
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return err;
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}
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