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1288f9b099
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt
Flip done handler is used to send the page flip event as soon as the
surface address is written as per the requirement of async flips.
The interrupt is disabled after the event is sent.
v2: -Change function name from icl_* to skl_* (Paulo)
-Move flip handler to this patch (Paulo)
-Remove vblank_put() (Paulo)
-Enable flip done interrupt for gen9+ only (Paulo)
-Enable flip done interrupt in power_well_post_enable hook (Paulo)
-Removed the event check in flip done handler to handle async
flips without pageflip events.
v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
-Make the pending vblank event NULL in the beginning of
flip_done_handler to remove sporadic WARN_ON that is seen.
v4: -Calculate timestamps using flip done time stamp and current
timestamp for async flips (Ville)
v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
static.(Reported-by: kernel test robot <lkp@intel.com>)
-Fix the typo in commit message.
v6: -Revert back to old time stamping code.
-Remove the break while calling skl_enable_flip_done. (Paulo)
v7: -Rebased.
v8: -Rebased.
v9: -Use struct drm_i915_private *i915 in new code. (Ville)
-Use intel_crtc instead of drm_crtc. (Ville)
-Do not mix the flip done and vblank hooks. (Ville)
v10: -Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-2-karthik.b.s@intel.com
167 lines
5.5 KiB
C
167 lines
5.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __I915_IRQ_H__
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#define __I915_IRQ_H__
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#include <linux/ktime.h>
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#include <linux/types.h>
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#include "display/intel_display.h"
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#include "i915_reg.h"
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struct drm_crtc;
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struct drm_device;
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struct drm_display_mode;
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struct drm_i915_private;
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struct intel_crtc;
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struct intel_uncore;
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void intel_irq_init(struct drm_i915_private *dev_priv);
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void intel_irq_fini(struct drm_i915_private *dev_priv);
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int intel_irq_install(struct drm_i915_private *dev_priv);
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void intel_irq_uninstall(struct drm_i915_private *dev_priv);
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u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
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enum pipe pipe);
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void
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i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
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u32 status_mask);
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void
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i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
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u32 status_mask);
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void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
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void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
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void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
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u32 mask,
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u32 bits);
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void ilk_update_display_irq(struct drm_i915_private *dev_priv,
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void
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ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
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{
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ilk_update_display_irq(dev_priv, bits, bits);
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}
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static inline void
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ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
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{
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ilk_update_display_irq(dev_priv, bits, 0);
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}
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void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe, u32 bits)
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{
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bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
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}
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static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
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enum pipe pipe, u32 bits)
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{
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bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
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}
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void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
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u32 interrupt_mask,
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u32 enabled_irq_mask);
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static inline void
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ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
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{
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ibx_display_interrupt_update(dev_priv, bits, bits);
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}
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static inline void
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ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
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{
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ibx_display_interrupt_update(dev_priv, bits, 0);
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}
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void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
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void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
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void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
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void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
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void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
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void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
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void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
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u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
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void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
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void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
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bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
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void intel_synchronize_irq(struct drm_i915_private *i915);
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int intel_get_crtc_scanline(struct intel_crtc *crtc);
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void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
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u8 pipe_mask);
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void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
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u8 pipe_mask);
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bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
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ktime_t *vblank_time, bool in_vblank_irq);
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u32 i915_get_vblank_counter(struct drm_crtc *crtc);
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u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
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int i8xx_enable_vblank(struct drm_crtc *crtc);
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int i915gm_enable_vblank(struct drm_crtc *crtc);
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int i965_enable_vblank(struct drm_crtc *crtc);
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int ilk_enable_vblank(struct drm_crtc *crtc);
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int bdw_enable_vblank(struct drm_crtc *crtc);
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void i8xx_disable_vblank(struct drm_crtc *crtc);
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void i915gm_disable_vblank(struct drm_crtc *crtc);
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void i965_disable_vblank(struct drm_crtc *crtc);
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void ilk_disable_vblank(struct drm_crtc *crtc);
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void bdw_disable_vblank(struct drm_crtc *crtc);
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void skl_enable_flip_done(struct intel_crtc *crtc);
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void skl_disable_flip_done(struct intel_crtc *crtc);
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void gen2_irq_reset(struct intel_uncore *uncore);
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void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
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i915_reg_t iir, i915_reg_t ier);
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void gen2_irq_init(struct intel_uncore *uncore,
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u32 imr_val, u32 ier_val);
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void gen3_irq_init(struct intel_uncore *uncore,
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i915_reg_t imr, u32 imr_val,
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i915_reg_t ier, u32 ier_val,
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i915_reg_t iir);
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#define GEN8_IRQ_RESET_NDX(uncore, type, which) \
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({ \
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unsigned int which_ = which; \
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gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
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GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
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})
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#define GEN3_IRQ_RESET(uncore, type) \
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gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
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#define GEN2_IRQ_RESET(uncore) \
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gen2_irq_reset(uncore)
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#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
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({ \
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unsigned int which_ = which; \
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gen3_irq_init((uncore), \
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GEN8_##type##_IMR(which_), imr_val, \
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GEN8_##type##_IER(which_), ier_val, \
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GEN8_##type##_IIR(which_)); \
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})
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#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
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gen3_irq_init((uncore), \
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type##IMR, imr_val, \
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type##IER, ier_val, \
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type##IIR)
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#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
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gen2_irq_init((uncore), imr_val, ier_val)
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#endif /* __I915_IRQ_H__ */
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