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a12562bb70
In preparation for changing how the driver handles 'mem_enable' in the CXL DVSEC control register. Merge the contents of cxl_hdm_decode_init() into cxl_dvsec_ranges() and rename the combined function cxl_hdm_decode_init(). The possible cleanups and fixes that result from this merge are saved for a follow-on change. Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/165291690027.1426646.10249756632415633752.stgit@dwillia2-xfh Signed-off-by: Dan Williams <dan.j.williams@intel.com>
344 lines
8.1 KiB
C
344 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2021 Intel Corporation. All rights reserved. */
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <cxlpci.h>
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#include <cxlmem.h>
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#include <cxl.h>
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#include "core.h"
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/**
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* DOC: cxl core pci
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*
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* Compute Express Link protocols are layered on top of PCIe. CXL core provides
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* a set of helpers for CXL interactions which occur via PCIe.
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*/
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static unsigned short media_ready_timeout = 60;
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module_param(media_ready_timeout, ushort, 0644);
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MODULE_PARM_DESC(media_ready_timeout, "seconds to wait for media ready");
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struct cxl_walk_context {
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struct pci_bus *bus;
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struct cxl_port *port;
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int type;
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int error;
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int count;
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};
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static int match_add_dports(struct pci_dev *pdev, void *data)
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{
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struct cxl_walk_context *ctx = data;
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struct cxl_port *port = ctx->port;
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int type = pci_pcie_type(pdev);
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struct cxl_register_map map;
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struct cxl_dport *dport;
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u32 lnkcap, port_num;
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int rc;
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if (pdev->bus != ctx->bus)
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return 0;
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if (!pci_is_pcie(pdev))
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return 0;
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if (type != ctx->type)
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return 0;
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if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
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&lnkcap))
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return 0;
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rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
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if (rc)
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dev_dbg(&port->dev, "failed to find component registers\n");
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port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
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dport = devm_cxl_add_dport(port, &pdev->dev, port_num,
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cxl_regmap_to_base(pdev, &map));
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if (IS_ERR(dport)) {
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ctx->error = PTR_ERR(dport);
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return PTR_ERR(dport);
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}
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ctx->count++;
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dev_dbg(&port->dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));
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return 0;
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}
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/**
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* devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port
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* @port: cxl_port whose ->uport is the upstream of dports to be enumerated
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*
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* Returns a positive number of dports enumerated or a negative error
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* code.
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*/
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int devm_cxl_port_enumerate_dports(struct cxl_port *port)
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{
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struct pci_bus *bus = cxl_port_to_pci_bus(port);
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struct cxl_walk_context ctx;
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int type;
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if (!bus)
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return -ENXIO;
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if (pci_is_root_bus(bus))
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type = PCI_EXP_TYPE_ROOT_PORT;
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else
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type = PCI_EXP_TYPE_DOWNSTREAM;
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ctx = (struct cxl_walk_context) {
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.port = port,
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.bus = bus,
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.type = type,
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};
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pci_walk_bus(bus, match_add_dports, &ctx);
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if (ctx.count == 0)
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return -ENODEV;
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if (ctx.error)
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return ctx.error;
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return ctx.count;
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_port_enumerate_dports, CXL);
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/*
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* Wait up to @media_ready_timeout for the device to report memory
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* active.
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*/
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int cxl_await_media_ready(struct cxl_dev_state *cxlds)
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{
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struct pci_dev *pdev = to_pci_dev(cxlds->dev);
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int d = cxlds->cxl_dvsec;
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bool active = false;
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u64 md_status;
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int rc, i;
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for (i = media_ready_timeout; i; i--) {
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u32 temp;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &temp);
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if (rc)
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return rc;
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active = FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp);
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if (active)
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break;
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msleep(1000);
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}
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if (!active) {
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dev_err(&pdev->dev,
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"timeout awaiting memory active after %d seconds\n",
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media_ready_timeout);
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return -ETIMEDOUT;
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}
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md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET);
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if (!CXLMDEV_READY(md_status))
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return -EIO;
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL);
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static int wait_for_valid(struct cxl_dev_state *cxlds)
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{
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struct pci_dev *pdev = to_pci_dev(cxlds->dev);
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int d = cxlds->cxl_dvsec, rc;
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u32 val;
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/*
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* Memory_Info_Valid: When set, indicates that the CXL Range 1 Size high
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* and Size Low registers are valid. Must be set within 1 second of
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* deassertion of reset to CXL device. Likely it is already set by the
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* time this runs, but otherwise give a 1.5 second timeout in case of
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* clock skew.
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*/
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rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val);
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if (rc)
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return rc;
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if (val & CXL_DVSEC_MEM_INFO_VALID)
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return 0;
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msleep(1500);
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rc = pci_read_config_dword(pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(0), &val);
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if (rc)
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return rc;
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if (val & CXL_DVSEC_MEM_INFO_VALID)
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return 0;
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return -ETIMEDOUT;
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}
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static bool __cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
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struct cxl_endpoint_dvsec_info *info)
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{
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struct cxl_register_map map;
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struct cxl_component_reg_map *cmap = &map.component_map;
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bool global_enable, retval = false;
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void __iomem *crb;
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u32 global_ctrl;
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/* map hdm decoder */
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crb = ioremap(cxlds->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
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if (!crb) {
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dev_dbg(cxlds->dev, "Failed to map component registers\n");
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return false;
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}
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cxl_probe_component_regs(cxlds->dev, crb, cmap);
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if (!cmap->hdm_decoder.valid) {
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dev_dbg(cxlds->dev, "Invalid HDM decoder registers\n");
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goto out;
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}
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global_ctrl = readl(crb + cmap->hdm_decoder.offset +
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CXL_HDM_DECODER_CTRL_OFFSET);
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global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE;
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/*
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* Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
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* [High,Low] when HDM operation is enabled the range register values
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* are ignored by the device, but the spec also recommends matching the
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* DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
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* are expected even though Linux does not require or maintain that
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* match.
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*/
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if (!global_enable && info->mem_enabled && info->ranges)
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goto out;
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retval = true;
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/*
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* Permanently (for this boot at least) opt the device into HDM
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* operation. Individual HDM decoders still need to be enabled after
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* this point.
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*/
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if (!global_enable) {
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dev_dbg(cxlds->dev, "Enabling HDM decode\n");
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writel(global_ctrl | CXL_HDM_DECODER_ENABLE,
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crb + cmap->hdm_decoder.offset +
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CXL_HDM_DECODER_CTRL_OFFSET);
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}
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out:
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iounmap(crb);
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return retval;
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}
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/**
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* cxl_hdm_decode_init() - Setup HDM decoding for the endpoint
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* @cxlds: Device state
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* @info: DVSEC Range cached enumeration
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*
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* Try to enable the endpoint's HDM Decoder Capability
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*/
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int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
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struct cxl_endpoint_dvsec_info *info)
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{
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struct pci_dev *pdev = to_pci_dev(cxlds->dev);
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int hdm_count, rc, i, ranges = 0;
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struct device *dev = &pdev->dev;
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int d = cxlds->cxl_dvsec;
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u16 cap, ctrl;
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if (!d) {
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dev_dbg(dev, "No DVSEC Capability\n");
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return -ENXIO;
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}
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rc = pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap);
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if (rc)
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return rc;
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rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
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if (rc)
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return rc;
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if (!(cap & CXL_DVSEC_MEM_CAPABLE)) {
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dev_dbg(dev, "Not MEM Capable\n");
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return -ENXIO;
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}
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/*
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* It is not allowed by spec for MEM.capable to be set and have 0 legacy
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* HDM decoders (values > 2 are also undefined as of CXL 2.0). As this
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* driver is for a spec defined class code which must be CXL.mem
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* capable, there is no point in continuing to enable CXL.mem.
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*/
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hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap);
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if (!hdm_count || hdm_count > 2)
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return -EINVAL;
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rc = wait_for_valid(cxlds);
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if (rc) {
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dev_dbg(dev, "Failure awaiting MEM_INFO_VALID (%d)\n", rc);
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return rc;
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}
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info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
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if (!info->mem_enabled)
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return 0;
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for (i = 0; i < hdm_count; i++) {
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u64 base, size;
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u32 temp;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp);
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if (rc)
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return rc;
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size = (u64)temp << 32;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp);
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if (rc)
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return rc;
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size |= temp & CXL_DVSEC_MEM_SIZE_LOW_MASK;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp);
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if (rc)
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return rc;
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base = (u64)temp << 32;
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rc = pci_read_config_dword(
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pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp);
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if (rc)
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return rc;
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base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK;
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info->dvsec_range[i] = (struct range) {
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.start = base,
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.end = base + size - 1
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};
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if (size)
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ranges++;
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}
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info->ranges = ranges;
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/*
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* If DVSEC ranges are being used instead of HDM decoder registers there
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* is no use in trying to manage those.
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*/
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if (!__cxl_hdm_decode_init(cxlds, info)) {
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dev_err(dev,
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"Legacy range registers configuration prevents HDM operation.\n");
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return -EBUSY;
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}
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return 0;
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}
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EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
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