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6b5e741e9a
Implement the mips_cdmm_phys_base() platform callback to provide a default Common Device Memory Map (CDMM) physical base address for the Pistachio SoC. This allows the CDMM in each VPE to be configured and probed for devices, such as the Fast Debug Channel (FDC). The physical address chosen is just below the default CPC address, which appears to also be unallocated. The FDC IRQ is also usable on Pistachio, and is routed through the GIC, so implement the get_c0_fdc_int() platform callback using gic_get_c0_fdc_int(), so the FDC driver doesn't have to fall back to polling. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Cc: linux-mips@linux-mips.org Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Patchwork: http://patchwork.linux-mips.org/patch/9749/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
138 lines
3.0 KiB
C
138 lines
3.0 KiB
C
/*
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* Pistachio platform setup
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*
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* Copyright (C) 2014 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <asm/cacheflush.h>
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#include <asm/dma-coherence.h>
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#include <asm/fw/fw.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-cpc.h>
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#include <asm/prom.h>
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#include <asm/smp-ops.h>
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#include <asm/traps.h>
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const char *get_system_type(void)
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{
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return "IMG Pistachio SoC";
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}
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static void __init plat_setup_iocoherency(void)
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{
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/*
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* Kernel has been configured with software coherency
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* but we might choose to turn it off and use hardware
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* coherency instead.
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*/
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if (mips_cm_numiocu() != 0) {
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/* Nothing special needs to be done to enable coherency */
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pr_info("CMP IOCU detected\n");
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hw_coherentio = 1;
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if (coherentio == 0)
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pr_info("Hardware DMA cache coherency disabled\n");
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else
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pr_info("Hardware DMA cache coherency enabled\n");
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} else {
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if (coherentio == 1)
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pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
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else
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pr_info("Software DMA cache coherency enabled\n");
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}
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}
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void __init plat_mem_setup(void)
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{
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if (fw_arg0 != -2)
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panic("Device-tree not present");
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__dt_setup_arch((void *)fw_arg1);
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strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
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plat_setup_iocoherency();
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}
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#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
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#define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
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phys_addr_t mips_cpc_default_phys_base(void)
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{
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return DEFAULT_CPC_BASE_ADDR;
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}
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phys_addr_t mips_cdmm_phys_base(void)
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{
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return DEFAULT_CDMM_BASE_ADDR;
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}
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static void __init mips_nmi_setup(void)
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{
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void *base;
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extern char except_vec_nmi;
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base = cpu_has_veic ?
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(void *)(CAC_BASE + 0xa80) :
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(void *)(CAC_BASE + 0x380);
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memcpy(base, &except_vec_nmi, 0x80);
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flush_icache_range((unsigned long)base,
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(unsigned long)base + 0x80);
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}
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static void __init mips_ejtag_setup(void)
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{
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void *base;
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extern char except_vec_ejtag_debug;
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base = cpu_has_veic ?
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(void *)(CAC_BASE + 0xa00) :
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(void *)(CAC_BASE + 0x300);
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memcpy(base, &except_vec_ejtag_debug, 0x80);
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flush_icache_range((unsigned long)base,
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(unsigned long)base + 0x80);
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}
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void __init prom_init(void)
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{
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board_nmi_handler_setup = mips_nmi_setup;
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board_ejtag_handler_setup = mips_ejtag_setup;
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mips_cm_probe();
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mips_cpc_probe();
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register_cps_smp_ops();
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}
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void __init prom_free_prom_memory(void)
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{
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}
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void __init device_tree_init(void)
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{
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if (!initial_boot_params)
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return;
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unflatten_and_copy_device_tree();
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}
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static int __init plat_of_setup(void)
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{
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if (!of_have_populated_dt())
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panic("Device tree not present");
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if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
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panic("Failed to populate DT");
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return 0;
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}
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arch_initcall(plat_of_setup);
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