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0d73297e48
ad193x devices support 96KHz and 192KHz sampling rates, when PLL/MCLK is referenced to 48kHz. Tested on ad1934. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20210803104825.2198335-1-codrin.ciubotariu@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
111 lines
3.5 KiB
C
111 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* AD193X Audio Codec driver
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*
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* Copyright 2010 Analog Devices Inc.
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*/
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#ifndef __AD193X_H__
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#define __AD193X_H__
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#include <linux/regmap.h>
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struct device;
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enum ad193x_type {
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AD193X,
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AD1933,
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AD1934,
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};
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extern const struct regmap_config ad193x_regmap_config;
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int ad193x_probe(struct device *dev, struct regmap *regmap,
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enum ad193x_type type);
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#define AD193X_PLL_CLK_CTRL0 0x00
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#define AD193X_PLL_POWERDOWN 0x01
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#define AD193X_PLL_INPUT_MASK 0x6
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#define AD193X_PLL_INPUT_256 (0 << 1)
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#define AD193X_PLL_INPUT_384 (1 << 1)
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#define AD193X_PLL_INPUT_512 (2 << 1)
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#define AD193X_PLL_INPUT_768 (3 << 1)
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#define AD193X_PLL_CLK_CTRL1 0x01
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#define AD193X_PLL_SRC_MASK 0x03
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#define AD193X_PLL_DAC_SRC_PLL 0
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#define AD193X_PLL_DAC_SRC_MCLK 1
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#define AD193X_PLL_CLK_SRC_PLL (0 << 1)
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#define AD193X_PLL_CLK_SRC_MCLK (1 << 1)
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#define AD193X_DAC_CTRL0 0x02
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#define AD193X_DAC_POWERDOWN 0x01
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#define AD193X_DAC_SR_MASK 0x06
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#define AD193X_DAC_SR_48 (0 << 1)
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#define AD193X_DAC_SR_96 (1 << 1)
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#define AD193X_DAC_SR_192 (2 << 1)
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#define AD193X_DAC_SERFMT_MASK 0xC0
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#define AD193X_DAC_SERFMT_STEREO (0 << 6)
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#define AD193X_DAC_SERFMT_TDM (1 << 6)
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#define AD193X_DAC_CTRL1 0x03
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#define AD193X_DAC_CHAN_SHFT 1
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#define AD193X_DAC_CHAN_MASK (3 << AD193X_DAC_CHAN_SHFT)
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#define AD193X_DAC_LCR_MASTER (1 << 4)
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#define AD193X_DAC_BCLK_MASTER (1 << 5)
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#define AD193X_DAC_LEFT_HIGH (1 << 3)
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#define AD193X_DAC_BCLK_INV (1 << 7)
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#define AD193X_DAC_FMT_MASK (AD193X_DAC_LCR_MASTER | \
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AD193X_DAC_BCLK_MASTER | AD193X_DAC_LEFT_HIGH | AD193X_DAC_BCLK_INV)
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#define AD193X_DAC_CTRL2 0x04
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#define AD193X_DAC_WORD_LEN_SHFT 3
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#define AD193X_DAC_WORD_LEN_MASK 0x18
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#define AD193X_DAC_MASTER_MUTE 1
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#define AD193X_DAC_CHNL_MUTE 0x05
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#define AD193X_DACL1_MUTE 0
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#define AD193X_DACR1_MUTE 1
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#define AD193X_DACL2_MUTE 2
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#define AD193X_DACR2_MUTE 3
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#define AD193X_DACL3_MUTE 4
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#define AD193X_DACR3_MUTE 5
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#define AD193X_DACL4_MUTE 6
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#define AD193X_DACR4_MUTE 7
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#define AD193X_DAC_L1_VOL 0x06
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#define AD193X_DAC_R1_VOL 0x07
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#define AD193X_DAC_L2_VOL 0x08
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#define AD193X_DAC_R2_VOL 0x09
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#define AD193X_DAC_L3_VOL 0x0a
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#define AD193X_DAC_R3_VOL 0x0b
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#define AD193X_DAC_L4_VOL 0x0c
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#define AD193X_DAC_R4_VOL 0x0d
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#define AD193X_ADC_CTRL0 0x0e
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#define AD193X_ADC_POWERDOWN 0x01
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#define AD193X_ADC_HIGHPASS_FILTER 1
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#define AD193X_ADCL1_MUTE 2
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#define AD193X_ADCR1_MUTE 3
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#define AD193X_ADCL2_MUTE 4
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#define AD193X_ADCR2_MUTE 5
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#define AD193X_ADC_CTRL1 0x0f
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#define AD193X_ADC_SERFMT_MASK 0x60
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#define AD193X_ADC_SERFMT_STEREO (0 << 5)
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#define AD193X_ADC_SERFMT_TDM (1 << 5)
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#define AD193X_ADC_SERFMT_AUX (2 << 5)
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#define AD193X_ADC_WORD_LEN_MASK 0x3
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#define AD193X_ADC_CTRL2 0x10
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#define AD193X_ADC_CHAN_SHFT 4
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#define AD193X_ADC_CHAN_MASK (3 << AD193X_ADC_CHAN_SHFT)
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#define AD193X_ADC_LCR_MASTER (1 << 3)
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#define AD193X_ADC_BCLK_MASTER (1 << 6)
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#define AD193X_ADC_LEFT_HIGH (1 << 2)
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#define AD193X_ADC_BCLK_INV (1 << 1)
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#define AD193X_ADC_FMT_MASK (AD193X_ADC_LCR_MASTER | \
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AD193X_ADC_BCLK_MASTER | AD193X_ADC_LEFT_HIGH | AD193X_ADC_BCLK_INV)
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#define AD193X_2_CHANNELS 0
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#define AD193X_4_CHANNELS 1
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#define AD193X_8_CHANNELS 2
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#define AD193X_16_CHANNELS 3
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#define AD193X_NUM_REGS 17
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#define AD193X_SYSCLK_PLL 0
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#define AD193X_SYSCLK_MCLK 1
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#endif
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