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fdd2c12e37
Now that sun4i PWM driver supports deasserting reset line and enabling bus clock, support for H6 PWM can be added. Note that while H6 PWM has two channels, only first one is wired to output pin. Second channel is used as a clock source to companion AC200 chip which is bundled into same package. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
533 lines
14 KiB
C
533 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for Allwinner sun4i Pulse Width Modulation Controller
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*
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* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
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*
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* Limitations:
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* - When outputing the source clock directly, the PWM logic will be bypassed
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* and the currently running period is not guaranteed to be completed
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/time.h>
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#define PWM_CTRL_REG 0x0
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#define PWM_CH_PRD_BASE 0x4
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#define PWM_CH_PRD_OFFSET 0x4
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#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
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#define PWMCH_OFFSET 15
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#define PWM_PRESCAL_MASK GENMASK(3, 0)
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#define PWM_PRESCAL_OFF 0
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#define PWM_EN BIT(4)
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#define PWM_ACT_STATE BIT(5)
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#define PWM_CLK_GATING BIT(6)
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#define PWM_MODE BIT(7)
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#define PWM_PULSE BIT(8)
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#define PWM_BYPASS BIT(9)
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#define PWM_RDY_BASE 28
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#define PWM_RDY_OFFSET 1
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#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
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#define PWM_PRD(prd) (((prd) - 1) << 16)
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#define PWM_PRD_MASK GENMASK(15, 0)
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#define PWM_DTY_MASK GENMASK(15, 0)
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#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
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#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
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#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
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#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
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static const u32 prescaler_table[] = {
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120,
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180,
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240,
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360,
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480,
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0,
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0,
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0,
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12000,
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24000,
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36000,
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48000,
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72000,
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0,
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0,
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0, /* Actually 1 but tested separately */
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};
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struct sun4i_pwm_data {
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bool has_prescaler_bypass;
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bool has_direct_mod_clk_output;
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unsigned int npwm;
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};
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struct sun4i_pwm_chip {
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struct pwm_chip chip;
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struct clk *bus_clk;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *base;
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spinlock_t ctrl_lock;
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const struct sun4i_pwm_data *data;
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unsigned long next_period[2];
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bool needs_delay[2];
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};
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static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct sun4i_pwm_chip, chip);
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}
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static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
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unsigned long offset)
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{
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return readl(chip->base + offset);
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}
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static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
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u32 val, unsigned long offset)
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{
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writel(val, chip->base + offset);
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}
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static void sun4i_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
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u64 clk_rate, tmp;
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u32 val;
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unsigned int prescaler;
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clk_rate = clk_get_rate(sun4i_pwm->clk);
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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/*
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* PWM chapter in H6 manual has a diagram which explains that if bypass
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* bit is set, no other setting has any meaning. Even more, experiment
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* proved that also enable bit is ignored in this case.
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*/
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if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
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sun4i_pwm->data->has_direct_mod_clk_output) {
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state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
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state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
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state->polarity = PWM_POLARITY_NORMAL;
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state->enabled = true;
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return;
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}
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if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
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sun4i_pwm->data->has_prescaler_bypass)
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prescaler = 1;
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else
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prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
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if (prescaler == 0)
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return;
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if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
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state->polarity = PWM_POLARITY_NORMAL;
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else
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state->polarity = PWM_POLARITY_INVERSED;
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if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
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BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
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state->enabled = true;
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else
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state->enabled = false;
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val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
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tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
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tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
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}
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static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
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const struct pwm_state *state,
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u32 *dty, u32 *prd, unsigned int *prsclr,
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bool *bypass)
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{
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u64 clk_rate, div = 0;
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unsigned int pval, prescaler = 0;
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clk_rate = clk_get_rate(sun4i_pwm->clk);
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*bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
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state->enabled &&
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(state->period * clk_rate >= NSEC_PER_SEC) &&
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(state->period * clk_rate < 2 * NSEC_PER_SEC) &&
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(state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
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/* Skip calculation of other parameters if we bypass them */
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if (*bypass)
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return 0;
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if (sun4i_pwm->data->has_prescaler_bypass) {
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/* First, test without any prescaler when available */
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prescaler = PWM_PRESCAL_MASK;
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/*
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* When not using any prescaler, the clock period in nanoseconds
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* is not an integer so round it half up instead of
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* truncating to get less surprising values.
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*/
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div = clk_rate * state->period + NSEC_PER_SEC / 2;
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do_div(div, NSEC_PER_SEC);
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if (div - 1 > PWM_PRD_MASK)
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prescaler = 0;
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}
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if (prescaler == 0) {
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/* Go up from the first divider */
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for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
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if (!prescaler_table[prescaler])
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continue;
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pval = prescaler_table[prescaler];
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div = clk_rate;
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do_div(div, pval);
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div = div * state->period;
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do_div(div, NSEC_PER_SEC);
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if (div - 1 <= PWM_PRD_MASK)
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break;
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}
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if (div - 1 > PWM_PRD_MASK)
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return -EINVAL;
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}
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*prd = div;
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div *= state->duty_cycle;
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do_div(div, state->period);
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*dty = div;
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*prsclr = prescaler;
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return 0;
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}
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static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
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struct pwm_state cstate;
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u32 ctrl, duty, period, val;
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int ret;
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unsigned int delay_us, prescaler;
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unsigned long now;
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bool bypass;
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pwm_get_state(pwm, &cstate);
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if (!cstate.enabled) {
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ret = clk_prepare_enable(sun4i_pwm->clk);
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if (ret) {
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dev_err(chip->dev, "failed to enable PWM clock\n");
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return ret;
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}
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}
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spin_lock(&sun4i_pwm->ctrl_lock);
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ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
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&bypass);
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if (ret) {
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dev_err(chip->dev, "period exceeds the maximum value\n");
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spin_unlock(&sun4i_pwm->ctrl_lock);
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if (!cstate.enabled)
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clk_disable_unprepare(sun4i_pwm->clk);
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return ret;
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}
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if (sun4i_pwm->data->has_direct_mod_clk_output) {
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if (bypass) {
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ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
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/* We can skip other parameter */
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sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
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spin_unlock(&sun4i_pwm->ctrl_lock);
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return 0;
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}
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ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
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}
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if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
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/* Prescaler changed, the clock has to be gated */
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ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
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ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
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ctrl |= BIT_CH(prescaler, pwm->hwpwm);
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}
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val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
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sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
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sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
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usecs_to_jiffies(cstate.period / 1000 + 1);
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sun4i_pwm->needs_delay[pwm->hwpwm] = true;
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if (state->polarity != PWM_POLARITY_NORMAL)
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ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
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else
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ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
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ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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if (state->enabled) {
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ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
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} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
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ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
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ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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}
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sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
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spin_unlock(&sun4i_pwm->ctrl_lock);
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if (state->enabled)
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return 0;
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if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
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clk_disable_unprepare(sun4i_pwm->clk);
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return 0;
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}
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/* We need a full period to elapse before disabling the channel. */
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now = jiffies;
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if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
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time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
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delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
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now);
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if ((delay_us / 500) > MAX_UDELAY_MS)
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msleep(delay_us / 1000 + 1);
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else
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usleep_range(delay_us, delay_us * 2);
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}
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sun4i_pwm->needs_delay[pwm->hwpwm] = false;
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spin_lock(&sun4i_pwm->ctrl_lock);
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ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
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ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
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ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
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sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
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spin_unlock(&sun4i_pwm->ctrl_lock);
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clk_disable_unprepare(sun4i_pwm->clk);
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return 0;
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}
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static const struct pwm_ops sun4i_pwm_ops = {
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.apply = sun4i_pwm_apply,
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.get_state = sun4i_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
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.has_prescaler_bypass = false,
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.npwm = 2,
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};
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static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
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.has_prescaler_bypass = true,
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.npwm = 2,
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};
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static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
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.has_prescaler_bypass = true,
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.npwm = 1,
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};
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static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
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.has_prescaler_bypass = true,
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.has_direct_mod_clk_output = true,
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.npwm = 2,
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};
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static const struct of_device_id sun4i_pwm_dt_ids[] = {
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{
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.compatible = "allwinner,sun4i-a10-pwm",
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.data = &sun4i_pwm_dual_nobypass,
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}, {
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.compatible = "allwinner,sun5i-a10s-pwm",
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.data = &sun4i_pwm_dual_bypass,
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}, {
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.compatible = "allwinner,sun5i-a13-pwm",
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.data = &sun4i_pwm_single_bypass,
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}, {
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.compatible = "allwinner,sun7i-a20-pwm",
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.data = &sun4i_pwm_dual_bypass,
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}, {
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.compatible = "allwinner,sun8i-h3-pwm",
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.data = &sun4i_pwm_single_bypass,
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}, {
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.compatible = "allwinner,sun50i-h6-pwm",
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.data = &sun50i_h6_pwm_data,
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}, {
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/* sentinel */
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},
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};
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MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
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static int sun4i_pwm_probe(struct platform_device *pdev)
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{
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struct sun4i_pwm_chip *pwm;
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struct resource *res;
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int ret;
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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pwm->data = of_device_get_match_data(&pdev->dev);
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if (!pwm->data)
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return -ENODEV;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pwm->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pwm->base))
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return PTR_ERR(pwm->base);
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/*
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* All hardware variants need a source clock that is divided and
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* then feeds the counter that defines the output wave form. In the
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* device tree this clock is either unnamed or called "mod".
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* Some variants (e.g. H6) need another clock to access the
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* hardware registers; this is called "bus".
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* So we request "mod" first (and ignore the corner case that a
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* parent provides a "mod" clock while the right one would be the
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* unnamed one of the PWM device) and if this is not found we fall
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* back to the first clock of the PWM.
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*/
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pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
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if (IS_ERR(pwm->clk)) {
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if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "get mod clock failed %pe\n",
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pwm->clk);
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return PTR_ERR(pwm->clk);
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}
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if (!pwm->clk) {
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pwm->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pwm->clk)) {
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if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "get unnamed clock failed %pe\n",
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pwm->clk);
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return PTR_ERR(pwm->clk);
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}
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}
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pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
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if (IS_ERR(pwm->bus_clk)) {
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if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "get bus clock failed %pe\n",
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pwm->bus_clk);
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return PTR_ERR(pwm->bus_clk);
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}
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pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
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if (IS_ERR(pwm->rst)) {
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|
if (PTR_ERR(pwm->rst) != -EPROBE_DEFER)
|
|
dev_err(&pdev->dev, "get reset failed %pe\n",
|
|
pwm->rst);
|
|
return PTR_ERR(pwm->rst);
|
|
}
|
|
|
|
/* Deassert reset */
|
|
ret = reset_control_deassert(pwm->rst);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
|
|
ERR_PTR(ret));
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* We're keeping the bus clock on for the sake of simplicity.
|
|
* Actually it only needs to be on for hardware register accesses.
|
|
*/
|
|
ret = clk_prepare_enable(pwm->bus_clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
|
|
ERR_PTR(ret));
|
|
goto err_bus;
|
|
}
|
|
|
|
pwm->chip.dev = &pdev->dev;
|
|
pwm->chip.ops = &sun4i_pwm_ops;
|
|
pwm->chip.base = -1;
|
|
pwm->chip.npwm = pwm->data->npwm;
|
|
pwm->chip.of_xlate = of_pwm_xlate_with_flags;
|
|
pwm->chip.of_pwm_n_cells = 3;
|
|
|
|
spin_lock_init(&pwm->ctrl_lock);
|
|
|
|
ret = pwmchip_add(&pwm->chip);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
|
|
goto err_pwm_add;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, pwm);
|
|
|
|
return 0;
|
|
|
|
err_pwm_add:
|
|
clk_disable_unprepare(pwm->bus_clk);
|
|
err_bus:
|
|
reset_control_assert(pwm->rst);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sun4i_pwm_remove(struct platform_device *pdev)
|
|
{
|
|
struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
ret = pwmchip_remove(&pwm->chip);
|
|
if (ret)
|
|
return ret;
|
|
|
|
clk_disable_unprepare(pwm->bus_clk);
|
|
reset_control_assert(pwm->rst);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sun4i_pwm_driver = {
|
|
.driver = {
|
|
.name = "sun4i-pwm",
|
|
.of_match_table = sun4i_pwm_dt_ids,
|
|
},
|
|
.probe = sun4i_pwm_probe,
|
|
.remove = sun4i_pwm_remove,
|
|
};
|
|
module_platform_driver(sun4i_pwm_driver);
|
|
|
|
MODULE_ALIAS("platform:sun4i-pwm");
|
|
MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
|
|
MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
|
|
MODULE_LICENSE("GPL v2");
|