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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 24 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.162703968@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
426 lines
10 KiB
C
426 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Imagination Technologies Pulse Width Modulator driver
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*
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* Copyright (c) 2014-2015, Imagination Technologies
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*
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* Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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/* PWM registers */
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#define PWM_CTRL_CFG 0x0000
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#define PWM_CTRL_CFG_NO_SUB_DIV 0
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#define PWM_CTRL_CFG_SUB_DIV0 1
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#define PWM_CTRL_CFG_SUB_DIV1 2
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#define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
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#define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
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#define PWM_CTRL_CFG_DIV_MASK 0x3
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#define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
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#define PWM_CH_CFG_TMBASE_SHIFT 0
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#define PWM_CH_CFG_DUTY_SHIFT 16
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#define PERIP_PWM_PDM_CONTROL 0x0140
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#define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
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#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
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#define IMG_PWM_PM_TIMEOUT 1000 /* ms */
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/*
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* PWM period is specified with a timebase register,
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* in number of step periods. The PWM duty cycle is also
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* specified in step periods, in the [0, $timebase] range.
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* In other words, the timebase imposes the duty cycle
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* resolution. Therefore, let's constraint the timebase to
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* a minimum value to allow a sane range of duty cycle values.
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* Imposing a minimum timebase, will impose a maximum PWM frequency.
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*
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* The value chosen is completely arbitrary.
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*/
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#define MIN_TMBASE_STEPS 16
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#define IMG_PWM_NPWM 4
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struct img_pwm_soc_data {
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u32 max_timebase;
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};
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struct img_pwm_chip {
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struct device *dev;
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struct pwm_chip chip;
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struct clk *pwm_clk;
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struct clk *sys_clk;
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void __iomem *base;
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struct regmap *periph_regs;
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int max_period_ns;
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int min_period_ns;
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const struct img_pwm_soc_data *data;
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u32 suspend_ctrl_cfg;
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u32 suspend_ch_cfg[IMG_PWM_NPWM];
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};
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static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct img_pwm_chip, chip);
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}
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static inline void img_pwm_writel(struct img_pwm_chip *chip,
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u32 reg, u32 val)
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{
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writel(val, chip->base + reg);
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}
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static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
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u32 reg)
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{
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return readl(chip->base + reg);
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}
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static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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u32 val, div, duty, timebase;
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unsigned long mul, output_clk_hz, input_clk_hz;
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struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
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unsigned int max_timebase = pwm_chip->data->max_timebase;
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int ret;
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if (period_ns < pwm_chip->min_period_ns ||
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period_ns > pwm_chip->max_period_ns) {
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dev_err(chip->dev, "configured period not in range\n");
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return -ERANGE;
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}
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input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
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output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
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mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
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if (mul <= max_timebase) {
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div = PWM_CTRL_CFG_NO_SUB_DIV;
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timebase = DIV_ROUND_UP(mul, 1);
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} else if (mul <= max_timebase * 8) {
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div = PWM_CTRL_CFG_SUB_DIV0;
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timebase = DIV_ROUND_UP(mul, 8);
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} else if (mul <= max_timebase * 64) {
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div = PWM_CTRL_CFG_SUB_DIV1;
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timebase = DIV_ROUND_UP(mul, 64);
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} else if (mul <= max_timebase * 512) {
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div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
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timebase = DIV_ROUND_UP(mul, 512);
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} else {
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dev_err(chip->dev,
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"failed to configure timebase steps/divider value\n");
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return -EINVAL;
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}
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duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
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ret = pm_runtime_get_sync(chip->dev);
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if (ret < 0)
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return ret;
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
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val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
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PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
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(timebase << PWM_CH_CFG_TMBASE_SHIFT);
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img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
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pm_runtime_mark_last_busy(chip->dev);
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pm_runtime_put_autosuspend(chip->dev);
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return 0;
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}
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static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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u32 val;
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struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
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int ret;
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ret = pm_runtime_get_sync(chip->dev);
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if (ret < 0)
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return ret;
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val |= BIT(pwm->hwpwm);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
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PERIP_PWM_PDM_CONTROL_CH_MASK <<
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PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
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return 0;
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}
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static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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u32 val;
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struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val &= ~BIT(pwm->hwpwm);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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pm_runtime_mark_last_busy(chip->dev);
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pm_runtime_put_autosuspend(chip->dev);
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}
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static const struct pwm_ops img_pwm_ops = {
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.config = img_pwm_config,
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.enable = img_pwm_enable,
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.disable = img_pwm_disable,
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.owner = THIS_MODULE,
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};
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static const struct img_pwm_soc_data pistachio_pwm = {
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.max_timebase = 255,
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};
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static const struct of_device_id img_pwm_of_match[] = {
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{
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.compatible = "img,pistachio-pwm",
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.data = &pistachio_pwm,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, img_pwm_of_match);
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static int img_pwm_runtime_suspend(struct device *dev)
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{
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struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
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clk_disable_unprepare(pwm_chip->pwm_clk);
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clk_disable_unprepare(pwm_chip->sys_clk);
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return 0;
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}
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static int img_pwm_runtime_resume(struct device *dev)
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{
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struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(pwm_chip->sys_clk);
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if (ret < 0) {
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dev_err(dev, "could not prepare or enable sys clock\n");
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return ret;
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}
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ret = clk_prepare_enable(pwm_chip->pwm_clk);
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if (ret < 0) {
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dev_err(dev, "could not prepare or enable pwm clock\n");
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clk_disable_unprepare(pwm_chip->sys_clk);
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return ret;
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}
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return 0;
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}
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static int img_pwm_probe(struct platform_device *pdev)
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{
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int ret;
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u64 val;
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unsigned long clk_rate;
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struct resource *res;
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struct img_pwm_chip *pwm;
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const struct of_device_id *of_dev_id;
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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pwm->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pwm->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pwm->base))
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return PTR_ERR(pwm->base);
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of_dev_id = of_match_device(img_pwm_of_match, &pdev->dev);
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if (!of_dev_id)
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return -ENODEV;
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pwm->data = of_dev_id->data;
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pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"img,cr-periph");
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if (IS_ERR(pwm->periph_regs))
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return PTR_ERR(pwm->periph_regs);
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pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
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if (IS_ERR(pwm->sys_clk)) {
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dev_err(&pdev->dev, "failed to get system clock\n");
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return PTR_ERR(pwm->sys_clk);
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}
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pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
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if (IS_ERR(pwm->pwm_clk)) {
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dev_err(&pdev->dev, "failed to get pwm clock\n");
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return PTR_ERR(pwm->pwm_clk);
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}
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pm_runtime_set_autosuspend_delay(&pdev->dev, IMG_PWM_PM_TIMEOUT);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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if (!pm_runtime_enabled(&pdev->dev)) {
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ret = img_pwm_runtime_resume(&pdev->dev);
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if (ret)
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goto err_pm_disable;
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}
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clk_rate = clk_get_rate(pwm->pwm_clk);
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if (!clk_rate) {
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dev_err(&pdev->dev, "pwm clock has no frequency\n");
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ret = -EINVAL;
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goto err_suspend;
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}
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/* The maximum input clock divider is 512 */
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val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;
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do_div(val, clk_rate);
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pwm->max_period_ns = val;
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val = (u64)NSEC_PER_SEC * MIN_TMBASE_STEPS;
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do_div(val, clk_rate);
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pwm->min_period_ns = val;
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &img_pwm_ops;
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pwm->chip.base = -1;
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pwm->chip.npwm = IMG_PWM_NPWM;
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ret = pwmchip_add(&pwm->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
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goto err_suspend;
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}
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platform_set_drvdata(pdev, pwm);
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return 0;
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err_suspend:
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if (!pm_runtime_enabled(&pdev->dev))
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img_pwm_runtime_suspend(&pdev->dev);
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err_pm_disable:
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pm_runtime_disable(&pdev->dev);
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pm_runtime_dont_use_autosuspend(&pdev->dev);
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return ret;
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}
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static int img_pwm_remove(struct platform_device *pdev)
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{
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struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
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u32 val;
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unsigned int i;
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int ret;
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ret = pm_runtime_get_sync(&pdev->dev);
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if (ret < 0)
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return ret;
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for (i = 0; i < pwm_chip->chip.npwm; i++) {
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val &= ~BIT(i);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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}
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pm_runtime_put(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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if (!pm_runtime_status_suspended(&pdev->dev))
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img_pwm_runtime_suspend(&pdev->dev);
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return pwmchip_remove(&pwm_chip->chip);
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}
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#ifdef CONFIG_PM_SLEEP
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static int img_pwm_suspend(struct device *dev)
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{
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struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
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int i, ret;
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if (pm_runtime_status_suspended(dev)) {
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ret = img_pwm_runtime_resume(dev);
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if (ret)
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return ret;
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}
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for (i = 0; i < pwm_chip->chip.npwm; i++)
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pwm_chip->suspend_ch_cfg[i] = img_pwm_readl(pwm_chip,
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PWM_CH_CFG(i));
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pwm_chip->suspend_ctrl_cfg = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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img_pwm_runtime_suspend(dev);
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return 0;
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}
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static int img_pwm_resume(struct device *dev)
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{
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struct img_pwm_chip *pwm_chip = dev_get_drvdata(dev);
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int ret;
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int i;
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ret = img_pwm_runtime_resume(dev);
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if (ret)
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return ret;
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for (i = 0; i < pwm_chip->chip.npwm; i++)
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img_pwm_writel(pwm_chip, PWM_CH_CFG(i),
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pwm_chip->suspend_ch_cfg[i]);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, pwm_chip->suspend_ctrl_cfg);
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for (i = 0; i < pwm_chip->chip.npwm; i++)
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if (pwm_chip->suspend_ctrl_cfg & BIT(i))
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regmap_update_bits(pwm_chip->periph_regs,
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PERIP_PWM_PDM_CONTROL,
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PERIP_PWM_PDM_CONTROL_CH_MASK <<
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PERIP_PWM_PDM_CONTROL_CH_SHIFT(i),
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0);
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if (pm_runtime_status_suspended(dev))
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img_pwm_runtime_suspend(dev);
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return 0;
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}
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#endif /* CONFIG_PM */
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static const struct dev_pm_ops img_pwm_pm_ops = {
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SET_RUNTIME_PM_OPS(img_pwm_runtime_suspend,
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img_pwm_runtime_resume,
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NULL)
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SET_SYSTEM_SLEEP_PM_OPS(img_pwm_suspend, img_pwm_resume)
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};
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static struct platform_driver img_pwm_driver = {
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.driver = {
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.name = "img-pwm",
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.pm = &img_pwm_pm_ops,
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.of_match_table = img_pwm_of_match,
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},
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.probe = img_pwm_probe,
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.remove = img_pwm_remove,
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};
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module_platform_driver(img_pwm_driver);
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MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
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MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
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MODULE_LICENSE("GPL v2");
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