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9d0a6fa6c5
HW guys say that it is not a cool idea to let device go into rc6 without proper 3d pipeline state. For each new uninitialized context, generate a valid null render state to be run on context creation. This patch introduces a skeleton with empty states. v2: - No need to vmap (Chris Wilson) - use .c files for state (Daniel Vetter) - no need to flush as i915_add_request does it - remove parameter for batch alloc size - don't wait for the init (Ben Widawsky) v3: - move to cpu/gpu (Chris Wilson) Tested-by: Kristen Carlson Accardi <kristen@linux.intel.com> (v1) Tested-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
195 lines
4.4 KiB
C
195 lines
4.4 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Mika Kuoppala <mika.kuoppala@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "intel_renderstate.h"
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struct i915_render_state {
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struct drm_i915_gem_object *obj;
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unsigned long ggtt_offset;
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void *batch;
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u32 size;
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u32 len;
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};
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static struct i915_render_state *render_state_alloc(struct drm_device *dev)
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{
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struct i915_render_state *so;
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struct page *page;
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int ret;
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so = kzalloc(sizeof(*so), GFP_KERNEL);
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if (!so)
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return ERR_PTR(-ENOMEM);
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so->obj = i915_gem_alloc_object(dev, 4096);
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if (so->obj == NULL) {
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ret = -ENOMEM;
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goto free;
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}
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so->size = 4096;
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ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0);
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if (ret)
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goto free_gem;
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BUG_ON(so->obj->pages->nents != 1);
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page = sg_page(so->obj->pages->sgl);
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so->batch = kmap(page);
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if (!so->batch) {
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ret = -ENOMEM;
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goto unpin;
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}
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so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj);
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return so;
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unpin:
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i915_gem_object_ggtt_unpin(so->obj);
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free_gem:
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drm_gem_object_unreference(&so->obj->base);
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free:
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kfree(so);
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return ERR_PTR(ret);
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}
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static void render_state_free(struct i915_render_state *so)
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{
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kunmap(so->batch);
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i915_gem_object_ggtt_unpin(so->obj);
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drm_gem_object_unreference(&so->obj->base);
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kfree(so);
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}
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static const struct intel_renderstate_rodata *
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render_state_get_rodata(struct drm_device *dev, const int gen)
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{
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switch (gen) {
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case 6:
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return &gen6_null_state;
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case 7:
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return &gen7_null_state;
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case 8:
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return &gen8_null_state;
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}
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return NULL;
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}
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static int render_state_setup(const int gen,
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const struct intel_renderstate_rodata *rodata,
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struct i915_render_state *so)
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{
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const u64 goffset = i915_gem_obj_ggtt_offset(so->obj);
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u32 reloc_index = 0;
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u32 * const d = so->batch;
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unsigned int i = 0;
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int ret;
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if (!rodata || rodata->batch_items * 4 > so->size)
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return -EINVAL;
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ret = i915_gem_object_set_to_cpu_domain(so->obj, true);
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if (ret)
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return ret;
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while (i < rodata->batch_items) {
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u32 s = rodata->batch[i];
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if (reloc_index < rodata->reloc_items &&
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i * 4 == rodata->reloc[reloc_index]) {
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s += goffset & 0xffffffff;
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/* We keep batch offsets max 32bit */
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if (gen >= 8) {
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if (i + 1 >= rodata->batch_items ||
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rodata->batch[i + 1] != 0)
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return -EINVAL;
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d[i] = s;
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i++;
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s = (goffset & 0xffffffff00000000ull) >> 32;
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}
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reloc_index++;
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}
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d[i] = s;
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i++;
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}
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ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
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if (ret)
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return ret;
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if (rodata->reloc_items != reloc_index) {
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DRM_ERROR("not all relocs resolved, %d out of %d\n",
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reloc_index, rodata->reloc_items);
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return -EINVAL;
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}
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so->len = rodata->batch_items * 4;
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return 0;
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}
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int i915_gem_render_state_init(struct intel_ring_buffer *ring)
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{
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const int gen = INTEL_INFO(ring->dev)->gen;
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struct i915_render_state *so;
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const struct intel_renderstate_rodata *rodata;
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u32 seqno;
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int ret;
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rodata = render_state_get_rodata(ring->dev, gen);
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if (rodata == NULL)
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return 0;
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so = render_state_alloc(ring->dev);
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if (IS_ERR(so))
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return PTR_ERR(so);
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ret = render_state_setup(gen, rodata, so);
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if (ret)
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goto out;
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ret = ring->dispatch_execbuffer(ring,
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i915_gem_obj_ggtt_offset(so->obj),
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so->len,
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I915_DISPATCH_SECURE);
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if (ret)
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goto out;
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ret = i915_add_request(ring, &seqno);
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out:
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render_state_free(so);
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return ret;
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}
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