Linus Torvalds 4df7c5fde3 RISC-V Fixes for 6.7-rc5 ... * A pair of fixes to the new module load-time relocation code. * A fix for hwprobe overflowing on rv32. * A fix for to correctly decode C.SWSP and C.SDSP, which manifests in misaligned access handling. * A fix for a boot-time shadow call stack initialization ordering issue. * A fix for Andes' errata probing, which was calling riscv_noncoherent_supported() too late in the boot process and triggering an oops. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmVzPZ8THHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiV0LD/0S5ehBNExoF5B/uByAV+5Bgjvee2gc UyYcPoFqhHrd3EUBRNO8bCWXphMpFe19HvR4DDjQwOxmSWKFN58TEjkLZQTmfNGX z/iRdwkwCKWjnjnGdRupJT7nlPWnXDVbwosxcnRhkxBBZRPA29kjf+Hqg+vF0pIQ JMXhUwcV6FrZrKszV/erjNp4L/B1N9uHb5CBMGaYBTaQzMzmcNsCGDZpJrZxlEV/ MESSwgZRc5fUEhCVyafXoq1VVnjC2yM1fgrigpNmilDDLXYZ6iHk8h19cX2Wk2Ns AJ7PX9PR/xuDyaxPD8ANCj/isxqf06T8r3rdSn6aNjP+nzrAoSUAgKQDZNyZclFj nymGD/ZvE3gCqoZ6eYJmA0a3qqxQYpL154F1jJiyB+lIUPiqKIQgc5ksLRNCdvF4 60wc4qKkBKc2PpxU+tD2rn9nl9pAOXiuDGyoT452I3W5SlXb1qDdd5g4hrOlYg4y tSmnzyoI2L6qQ+Gux7TCAzTMTrBsSpMkH8uuPRFvk9DmV6bLsUHIlh/hGmqTQBdr eZM4vO9Xi1haF8THeiuf4T1PgTfG7qFGpzs3nZwz16WQKd4tm5Qe6Ms3oDa1RM9D ZX7feTdw859Pz6ULsm8QMTYn3mBKraUz1EdiNClsKFVBTw722pCk8VJhJbjWFQpZ h9IAyKdQjNeTEA== =Hb40 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - A pair of fixes to the new module load-time relocation code - A fix for hwprobe overflowing on rv32 - A fix for to correctly decode C.SWSP and C.SDSP, which manifests in misaligned access handling - A fix for a boot-time shadow call stack initialization ordering issue - A fix for Andes' errata probing, which was calling riscv_noncoherent_supported() too late in the boot process and triggering an oops * tag 'riscv-for-linus-6.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: errata: andes: Probe for IOCP only once in boot stage riscv: Fix SMP when shadow call stacks are enabled dt-bindings: perf: riscv,pmu: drop unneeded quotes riscv: fix misaligned access handling of C.SWSP and C.SDSP RISC-V: hwprobe: Always use u64 for extension bits Support rv32 ULEB128 test riscv: Correct type casting in module loading riscv: Safely remove entries from relocation list		2023-12-08 09:03:54 -08:00
..
bindings	RISC-V Fixes for 6.7-rc5	2023-12-08 09:03:54 -08:00
changesets.rst
dynamic-resolution-notes.rst
index.rst
kernel-api.rst
of_unittest.rst
overlay-notes.rst
usage-model.rst	docs: dt: fix documented Primecell compatible string	2023-06-08 07:31:59 -06:00