mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
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f15cbe6f1a
This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
191 lines
5.5 KiB
C
191 lines
5.5 KiB
C
#ifndef __ASM_SH_SMC37C93X_H
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#define __ASM_SH_SMC37C93X_H
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/*
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* linux/include/asm-sh/smc37c93x.h
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*
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* Copyright (C) 2000 Kazumoto Kojima
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*
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* SMSC 37C93x Super IO Chip support
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*/
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/* Default base I/O address */
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#define FDC_PRIMARY_BASE 0x3f0
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#define IDE1_PRIMARY_BASE 0x1f0
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#define IDE1_SECONDARY_BASE 0x170
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#define PARPORT_PRIMARY_BASE 0x378
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#define COM1_PRIMARY_BASE 0x2f8
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#define COM2_PRIMARY_BASE 0x3f8
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#define RTC_PRIMARY_BASE 0x070
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#define KBC_PRIMARY_BASE 0x060
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#define AUXIO_PRIMARY_BASE 0x000 /* XXX */
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/* Logical device number */
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#define LDN_FDC 0
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#define LDN_IDE1 1
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#define LDN_IDE2 2
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#define LDN_PARPORT 3
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#define LDN_COM1 4
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#define LDN_COM2 5
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#define LDN_RTC 6
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#define LDN_KBC 7
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#define LDN_AUXIO 8
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/* Configuration port and key */
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#define CONFIG_PORT 0x3f0
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#define INDEX_PORT CONFIG_PORT
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#define DATA_PORT 0x3f1
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#define CONFIG_ENTER 0x55
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#define CONFIG_EXIT 0xaa
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/* Configuration index */
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#define CURRENT_LDN_INDEX 0x07
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#define POWER_CONTROL_INDEX 0x22
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#define ACTIVATE_INDEX 0x30
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#define IO_BASE_HI_INDEX 0x60
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#define IO_BASE_LO_INDEX 0x61
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#define IRQ_SELECT_INDEX 0x70
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#define DMA_SELECT_INDEX 0x74
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#define GPIO46_INDEX 0xc6
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#define GPIO47_INDEX 0xc7
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/* UART stuff. Only for debugging. */
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/* UART Register */
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#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
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#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
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#define UART_IER 0x2 /* Interrupt Enable Register */
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#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
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#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
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#define UART_LCR 0x6 /* Line Control Register */
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#define UART_MCR 0x8 /* MODEM Control Register */
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#define UART_LSR 0xa /* Line Status Register */
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#define UART_MSR 0xc /* MODEM Status Register */
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#define UART_SCR 0xe /* Scratch Register */
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#define UART_DLL 0x0 /* Divisor Latch (LS) */
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#define UART_DLM 0x2 /* Divisor Latch (MS) */
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#ifndef __ASSEMBLY__
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typedef struct uart_reg {
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volatile __u16 rbr;
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volatile __u16 ier;
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volatile __u16 iir;
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volatile __u16 lcr;
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volatile __u16 mcr;
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volatile __u16 lsr;
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volatile __u16 msr;
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volatile __u16 scr;
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} uart_reg;
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#endif /* ! __ASSEMBLY__ */
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/* Alias for Write Only Register */
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#define thr rbr
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#define tcr iir
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/* Alias for Divisor Latch Register */
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#define dll rbr
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#define dlm ier
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#define fcr iir
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/* Interrupt Enable Register */
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#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
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#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
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#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
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#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
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/* Interrupt Ident Register */
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#define IIR_IP 0x0100 /* "0" if Interrupt Pending */
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#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
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#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
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#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
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#define IIR_FIFO 0xc000 /* FIFOs enabled */
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/* FIFO Control Register */
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#define FCR_FEN 0x0100 /* FIFO enable */
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#define FCR_RFRES 0x0200 /* Receiver FIFO reset */
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#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
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#define FCR_DMA 0x0800 /* DMA mode select */
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#define FCR_RTL 0x4000 /* Receiver triger (LSB) */
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#define FCR_RTM 0x8000 /* Receiver triger (MSB) */
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/* Line Control Register */
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#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
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#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
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#define LCR_STB 0x0400 /* Number of Stop Bits */
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#define LCR_PEN 0x0800 /* Parity Enable */
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#define LCR_EPS 0x1000 /* Even Parity Select */
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#define LCR_SP 0x2000 /* Stick Parity */
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#define LCR_SB 0x4000 /* Set Break */
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#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
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/* MODEM Control Register */
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#define MCR_DTR 0x0100 /* Data Terminal Ready */
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#define MCR_RTS 0x0200 /* Request to Send */
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#define MCR_OUT1 0x0400 /* Out 1 */
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#define MCR_IRQEN 0x0800 /* IRQ Enable */
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#define MCR_LOOP 0x1000 /* Loop */
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/* Line Status Register */
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#define LSR_DR 0x0100 /* Data Ready */
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#define LSR_OE 0x0200 /* Overrun Error */
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#define LSR_PE 0x0400 /* Parity Error */
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#define LSR_FE 0x0800 /* Framing Error */
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#define LSR_BI 0x1000 /* Break Interrupt */
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#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
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#define LSR_TEMT 0x4000 /* Transmitter Empty */
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#define LSR_FIFOE 0x8000 /* Receiver FIFO error */
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/* MODEM Status Register */
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#define MSR_DCTS 0x0100 /* Delta Clear to Send */
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#define MSR_DDSR 0x0200 /* Delta Data Set Ready */
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#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
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#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
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#define MSR_CTS 0x1000 /* Clear to Send */
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#define MSR_DSR 0x2000 /* Data Set Ready */
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#define MSR_RI 0x4000 /* Ring Indicator */
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#define MSR_DCD 0x8000 /* Data Carrier Detect */
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/* Baud Rate Divisor */
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#define UART_CLK (1843200) /* 1.8432 MHz */
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#define UART_BAUD(x) (UART_CLK / (16 * (x)))
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/* RTC register definition */
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#define RTC_SECONDS 0
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#define RTC_SECONDS_ALARM 1
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#define RTC_MINUTES 2
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#define RTC_MINUTES_ALARM 3
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#define RTC_HOURS 4
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#define RTC_HOURS_ALARM 5
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#define RTC_DAY_OF_WEEK 6
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#define RTC_DAY_OF_MONTH 7
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#define RTC_MONTH 8
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#define RTC_YEAR 9
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#define RTC_FREQ_SELECT 10
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# define RTC_UIP 0x80
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# define RTC_DIV_CTL 0x70
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/* This RTC can work under 32.768KHz clock only. */
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# define RTC_OSC_ENABLE 0x20
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# define RTC_OSC_DISABLE 0x00
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#define RTC_CONTROL 11
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# define RTC_SET 0x80
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# define RTC_PIE 0x40
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# define RTC_AIE 0x20
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# define RTC_UIE 0x10
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# define RTC_SQWE 0x08
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# define RTC_DM_BINARY 0x04
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# define RTC_24H 0x02
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# define RTC_DST_EN 0x01
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#endif /* __ASM_SH_SMC37C93X_H */
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